|I have a wide range of research interests from system level design to low level circuit performance modeling. Some of the recent topics include:
- Architectural Techniques for Mitigating Process Variation
- Process variation modeling/mitigation in the 3D Integration era
- Process variation modeling/mitigation for cache structures
- Interconnect Networks for Chip Multi-Processors
- Efficient hierarchical network topology design for many-core CMPs
- Adopting emerging signaling technologies for Network-on-Chip
- Network-on-Chip evaluation methodologies, evaluation framework.
- Empathic Computer Architectures
- Human-aware /Satisfaction-directed low-power techniques
- Design Automation for Neuroscience Simulation Platform
- Simulator for Early Stages in Rat Whisker Neural Circuits
While I enjoy the variety of perspectives from these projects, I am trying to focus on two of these topics that interest me most:
(1) On-Chip network evaluation methodology / Traffic Characterization
The prospect of many-core CMPs calls for research in high-performance on-chip communication fabrics. In this process, adopting accurate evaluation methodolgy is fundamentally important . However, traditional evaluation methodologies are inherently limited by either humongous simulation time or drastically simplified assumptions. By carefully studying the nature of on-chip traffic load/pattern, I aim to construct an accurate yet efficient evaluation framework that scales well with the booming of core count on a chip.
(2) Impact of process variation in 3D integration era.
Process variation has been a hot topic around for some time. However, the introduction of 3D integration yields new challenges and opportunities. Novel architectural techniques are needed to mitigate the impact of process variation while taking into account the new complications like pre-stacking testing, heat dissipation, etc. Thorough evaluation will be critical to the establishment of any proposed technique.