Unit Delay Resettable (Fixed-Point Blockset)

Fixed-Point Blockset

Unit Delay Resettable

Delay a signal one sample period, with an external Boolean reset

Library

Delays & Holds

Description

The Unit Delay Resettable block delays a signal one sample period.

The block can reset its state based on an external reset signal R. The block has two input ports, one for the input signal u and the other for the external reset signal R. When the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state to the initial condition, specified by the Initial condition parameter, and outputs that state delayed by one time step.

You specify the time between samples with the Sample time parameter. A setting of -1 means the Sample time is inherited.

Parameters and Dialog Box

Initial condition: The initial output of the simulation.
Sample time: Sample time.

Characteristics

Input Port u
Any data type supported by the blockset

Input Port R
Any data type supported by the blockset

Output Port
Same as the input u

Direct Feedthrough
No, of the input port
Yes, of the reset port

Scalar Expansion
Yes

Input Port `u`	Any data type supported by the blockset
Input Port `R`	Any data type supported by the blockset
Output Port	Same as the input `u`
Direct Feedthrough	No, of the input port Yes, of the reset port
Scalar Expansion	Yes

Unit Delay External IC Unit Delay Resettable External IC