Unit Delay Enabled Resettable (Fixed-Point Blockset)

Delay a signal one sample period, if the external enable signal is on, with an external Boolean reset

Library

Delays & Holds

Description

The Unit Delay Enabled Resettable block combines the features of the Unit Delay Enabled and Unit Delay Resettable blocks.

The block can reset its state based on an external reset signal R. When the enable signal E is on and the reset signal R is false, the block outputs the input signal delayed by one sample period.

When the enable signal E is on and the reset signal R is true, the block resets the current state to the initial condition, specified by the Initial condition parameter, and outputs that state delayed by one sample period.

When the enable signal is off, the block is disabled, and the state and output do not change except for resets. The enable signal is on when E is not 0, and off when E is 0.

You specify the time between samples with the Sample time parameter. A setting of -1 means the Sample time is inherited.

Parameters and Dialog Box

Initial condition: The initial output of the simulation.
Sample time: Sample time.

Characteristics

Input Port u
Any data type supported by the blockset

Input Port E
Any data type supported by the blockset

Input Port R
Any data type supported by the blockset

Output Port
Same as the input u

Direct Feedthrough
No, of the input port
No, of the enable port
Yes, of the reset port

Scalar Expansion
Yes

Input Port `u`	Any data type supported by the blockset
Input Port `E`	Any data type supported by the blockset
Input Port `R`	Any data type supported by the blockset
Output Port	Same as the input `u`
Direct Feedthrough	No, of the input port No, of the enable port Yes, of the reset port
Scalar Expansion	Yes

Unit Delay Enabled External IC Unit Delay Enabled Resettable External IC