This research project seeks to develop a complete adaptive solution for general purpose computing systems. It includes efforts in adaptive computer architectures, configuration management, high-level compilation, template based physical design, and military applications of adaptive computing. During the past year, we have developed and fabricated the Chimaera Logic Array. Chimaera provides an architecture for supporting very high-performance datapaths while tightly coupled to a host processor. We have demonstrated 1-2 orders of magnitude speedup on image processing and other tasks. We have also included architectural features to speed up carry computations by a factor of 3. We have developed caching and prefetching techniques for accelerating run-time reconfiguration. We have investigated compression techniques based around the Xilinx 6200 Wildcard hardware achieves a factor of 4 compression, with an additional factor of 2 achievable via Don't Care discovery. We have worked on the GCC based C compiler for the Chimaera system. We have developed a procedure to build a data flow expression tree within the GCC framework and use pattern matching to replace certain data flow expressions with CHIMAERA instructions. We have also performed a lot of work on compiler optimizations for C programs. We have completed development of floorplanning CAD tool where not all module information is available, or even worse, part of the provided information is inaccurate. This is used for speculative floorplanning, and is an important tool for addressing logic placement in FPGAs to support run-time reconfiguration. We have show that, for example, with up to 30 input uncertainty an area estimate with less than 7
This work has been supported by DARPA, and has supported 6 Ph.D. students (one female), 3 M.S. students, and 2 undergraduate students. One M.S. student has graduated (Matt Hosler).