The goals of this subtask were to develop a coherent theory of behavioral level power estimation, to develop a practical methodology for behavioral level power estimation, to develop a software tool for behavioral level power estimation, and to study the interaction between floorplanning and high-level synthesis as it relates to power estimation and synthesis.
Our research addressed the need for behavioral level power-driven design tools. First, a novel method of capturing switching information during behavioral level simulation was developed. Next, that information is shown useful for optimizing low-power datapaths. In addition, a new method of parallelizing loops is presented, which can result in lower power by achieving greater throughput and therefore requiring a lower voltage. Subsequently, the issue of estimating capacitance is taken up and a new floor planning based solution was given. Finally, the system used for gathering experimental data was described in detail. Each topic was supported by empirical results.
This research was supported by Motorola, and NSF, and resulted in 12 journal papers, 8 conference papers, supported 3 M.S. students (one female), 3 Ph.D. students, and 2 undergraduate students. One Ph.D. student (James Crenshaw) and one M.S. student (Maogang Wang) graduated. One of the undergraduate students supported, Sam King, received an honorable mention in Computing Research Association Outstanding Male Undergraduate Competition.