LIST OF PUBLICATIONS

The researchers in the Center published numerous papers in books, journals and conferences. The publications of the three most active members of the Center, Prof. Banerjee, Prof. Choudhary and Prof. Taylor, are listed below.

• D. J. Palermo, E. W. Hodges, and P. Banerjee, ``Dynamic Data Partitioning for Distributed Memory Multicomputers,'' chapter in Languages, Compilation Techniques, and Runtime Systems for Scalable Parallel Systems (Recent Advances and Future Prespectives Editors: S. Pande and D. P. Agarwal, Springer Verlag Publishers, 1997.
• E. Rudnick, V. Chickermane, P. Banerjee, J. H. Patel, ``Sequential Circuit Testability Enhancement Using a Non-scan Approach,'' IEEE Transactions on VLSI Systems, to appear, 1996.
• A. Roy-Chowdhury and P. Banerjee, ``Algorithm-based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems,'' IEEE Trans. Computers, to appear, 1996.
• K. McPherson and P. Banerjee, ``Parallel Algorithms for VLSI Layout Verification,'' Journal of Parallel and Distributed Computing, Vol. 36, no. 2, Sep. 1996, pp. 156-172.
• D. Palermo, E. W. Hodges and P. Banerjee, ``Dynamic Data Partitioning for Distributed Memory Multicomputers,'' Journal of Parallel and Distributed Computing (Special Issue on Compilation Techniques for Distributed Memory Systems) November 1, 1996, Vol. 38, no. 2, pp. 158-175.
• S. Ramaswamy, B. Simons and P. Banerjee, ``Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers,'' Journal of Parallel and Distributed Computing (Special Issue on Compilation Techniques for Distributed Memory Systems) November 1, 1996, Vol. 38, no. 2, pp. 217-228.
• S. Ramaswamy, S. Sapatnekar, and P. Banerjee, ``A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers,'' IEEE Trans. Parallel and Distributed Systems, Vol. 8, No. 11, November 1997.
• B. Ramkumar and P. Banerjee, ``ProperTEST: A Portable Parallel Test Generator for Sequential Circuits,'' IEEE Trans. Computer-Aided Design, to appear, 1997.
• G. Hasteer and P. Banerjee, ``A Parallel Algorithm for State Assignment of Finite State Machines,'' IEEE Transactions on Computers, to appear, 1997.
• V. Krishnaswamy, R. Gupta and P. Banerjee, ``Implications of VHDL Timing Models on SImulation and Software Synthesis,'' Journal of Systems Architecture, to appear, 1997.
• G. Hasteer and P. Banerjee, ``Simulated Annealing Based Parallel State Assignment for Finite State Machines,'' Journal of Parallel and Dist. Computing, Vol. 43, Jun. 1997.
• J. A. Chandy, S. Kim, B. Ramkumar, S. Parkes, and P. Banerjee ``An Evaluation of Parallel Simulated Annealing Strategies with Applications to Standard Cell Placement'', IEEE Trans. on Computer Aided Design, Vol. 16, No. 4, pp. 398-410, April 1997.
• P. Prabhakaran and P. Banerjee, ``Parallel Algorithms for Force-Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs,'' Proc. Int. Conf. Computer Design (ICCD-96), Austin, TX, Oct. 1996.
• D. Palermo, E. W. Hodges, and P. Banerjee, ``Techniques for Selecting and Analyzing Data Distributions,'' Workshop on Challenges in Compiling for Scalable Parallel Systems, New Orleans, LA, Oct. 1996.
• K. McPherson and P. Banerjee, ``Integrating Task and Data Parallelism in an Irregular Application: A Case Study'', Proc. Symp. on Parallel and Distributed Processing, New Orleans, LA, Oct. 1996, pp. 208-213.
• V. Krishnaswamy, R. Gupta, P. Banerjee, ``A Procedure for Software Synthesis from VHDL Models,'' Proc. of Asia-Pacific Design Automation Conf., Tokyo, JAPAN, Jan. 1997.
• G. Hasteer and P. Banerjee, ``Simulated Annealing Based Parallel State Assignment for Finite State Machines,'' Proc. Int. Conf. VLSI Design (VLSI-97), Hyderabad, INDIA, Jan. 1997.
• D. Krishnaswamy, M. S. Hsiao, V. Saxena, E. M. Rudnick, P. Banerjee, and J. Patel,''Parallel Genetic Algorithms for Simulation-based Sequential Circuit Test Generation,'' Proc. Int. Conf. VLSI Design (VLSI-97),, Hyderabad, INDIA, Jan. 1997.
• J. G. Holm, S. Parkes, and P. Banerjee, ``Performance Evaluation of a C++ Library Based Multithreaded System,'' Hawaii Int. Conf. on System Sciences, Maui, HA, Jan. 1997.
• V. Krishnaswamy, R. K. Gupta, and P. Banerjee, ``A Procedure for Software Synthesis from VHDL Models,'' Asia South Pacific Design Automation Conference, Japan, April 1997.
• S. Roy and P. Banerjee, ``A Comparison of Parallel approaches for Algebraic Factorization in Logic Synthesis'', Proc. Int. Parallel Processing Symposium (IPPS97), April 1997, Geneva, Switzerland.
• Z. Xing, J. Chandy, and P. Banerjee, ``Parallel Global Routing for Standard Cells,'' Proc. Int. Parallel Processing Symposium (IPPS-97), April 1997, Geneva, Switzerland.
• D. Krishnaswamy, P. Banerjee, E. Rudnick, and P. Banerjee, ``SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation,'' Proc. IEEE VLSI Test Symp., Monterey, CA, Apr. 1997.
• S. Roy and P. Banerjee, ``An L-Shaped Partitioning-Based Algebraic Factorization Algorithm Proc. Int. Symp. on Circuits and Systems (ISCAS-97), Hong Kong, Jun. 1997.
• D. Krishnaswamy, P. Banerjee, E. Rudnick and J. Patel, ``Asynchronous Parallel Algorithms for Test Set Partitioned Parallel Fault Simulation,'' Proc. Workshop on Parallel and Distributed Simulation (PADS-97), Jun. 1997.
• G. Hasteer, A. Mathur, P. Banerjee, ``An Efficient Assertion Checker for Combinational Properties,'' Proc. Design Automation Conference (DAC97), Jun. 1997.
• J. G. Holm, J. Chandy, G. Hasteer, V. Krishnaswamy, S. Parkes, S. Roy, and P. Banerjee, "Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General-Purpose Multiprocessors," Proc. International Conference on Supercomputing (ICS-97), Vienna, AUSTRIA, July 1997.
• D. Krishnaswamy and P. Banerjee, ``Exploiting Task and Data Parallelism in Parallel Hough and Radon Transforms,'' Proc. Int. Conference on Parallel Processing (ICPP-97) Bloomingdale, IL, Aug. 1997.
• V. Krishnaswamy, G. Hasteer, and P. Banerjee, ``Load Balancing and Workload Minimization of Overlapping Parallel Tasks,'' Proc. Int. Conference on Parallel Processing (ICPP-97) Bloomingdale, IL, Aug. 1997.
• A. Lain and P. Banerjee, ``Compiler and Run-Time Support for Exploiting Regularity within Irregular Applicatons,'' IEEE Trans. Parallel and Dist. Syst., submitted June 1996.
• S. Roy and P. Banerjee, ``A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis'', submitted IEEE Trans. Computers, 1996
• S. Parkes, J. G. Holm, J. A. Chandy, and P. Banerjee, ``A Class Library Approach to Concurrent Object Oriented Programming with Applications to VLSI CAD,'' submitted Journal of Parallel and Distributed Computing, July 1997.
• D. J. Palermo, E. Su, J. A. Chandy, and P. Banerjee, ``Communication Optimizations for Distributed-Memory Multicomputers,'' submitted Journ. on Parallel and Distributed Computing, revised Jan 1996 original submitted Oct 94.
• J. Chandy and P. Banerjee, ``A Parallel Circuit Partitioned Algorithm for Timing-Driven Standard Cell Placement,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Sep. 1996, submitted.
• Z. Xing, J. Chandy and P. Banerjee, ``Parallel Global Routing for Standard Cells,'' IEEE Trans. Computer-Aided Design (TCAD), Submitted Sep. 1996.
• J. G. Holm, J. Chandy, G. Hasteer, V. Krishnaswamy, S. Parkes, S. Roy, and P. Banerjee, ``Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General-Purpose Multiprocessors,'' IEEE Transactions on Parallel and Distributed Systems, submitted Mar. 1997.
• P. Prabhakaran and P. Banerjee, ``Parallel Algorithms for Force-Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs,'' IEEE Transactions on Computers, submitted Mar. 1997.
• V. Krishnaswamy, G. Hasteer, and P. Banerjee, ``Automatic Parallelization of Compiled Event Driven VHDL Simulation,'' IEEE Transactions on CAD, submitted April 1997.
• M. Kandemir, A. Choudhary, J. Ramanujam, and R. Bordawekar, ``Compilation Techniques for Out-of-Core Parallel Computations,'' Journal of Parallel Programming, to appear.
• M. Kandaswamy, M. Kandemir, A. Choudhary and D. Bernholdt, ``An Experimental Study to Analyze and Optimize Hartree-Fock Application's I/O With PASSION,'' International Journal of Supercomputing, to appear.
• S. Adve, D. Burger, R. Eigenmann, A. Rawsthorne, M. Smith, C. Gebotys, M. Kandemir, D. Kalilja, A. Choudhary, J. Fang, P. Yew, ``The Interaction of Architecture and Compilation Technology for High-Performance Processor Design,'' IEEE Computer Magazine, to appear.
• D. Jadav, C. Srinilta, A. Choudhary, and P. B. Berra, ``An Evaluation of Design Trade-Offs in a High-Performance, Media-On-Demand Server,'' ACM Multimedia Systems Journal, Vol. 5, Jan. 1997, pp. 53-68.
• R. Thakur and A. Choudhary, ``An Extended Two-Phase Method for Accessing Sections of Out-of-Core Arrays,'' Journal of Scientific Programming, Vol. 5, No. 4, PP. 301-317, Winter 1996.
• S. Chaudhry and A. Choudhary, ``Time Dependent Priority Scheduling for Guaranteed Service Connections,'' Proc. 6th International Conference on Computer Communications and Networks, Las Vegas, NV, Sept. 1997.
• M. Kandemir, J. Ramanujam, and A. Choudhary, ``Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines,''PACT'97, to appear.
• M. Kandemir, A. Choudhary, J. Ramanujam, and M. Kandaswamy, ``A Unified Compiler Algorithm for Optimizing Locality, Parallelism and Communication in Out-of-Core Computations,'' IOPADS'97, to appear.
• M. Kandaswamy, M. Kandemir, A. Choudhary, and D. Bernholdt, ``Optimization and Evaluation of Hartree-Fock Application's I/O With PASSION,'' SC '97, to appear.
• M. Kandemir, M. Kandaswamy, and A. Choudhary, ``Global I/O Optimizations for Out-of-Core Computations,'' HiPC '97, to appear.
• M. Kandemir, J. Ramanujam, and A. Choudhary, ``Improving the Performance of Out-of-Core Computations,'' Proc. International Conference on Parallel Processing, Bloomingdale, IL, August 1997.
• M. Kandemir, J. Ramanujam, and A. Choudhary, ``Optimizing Out-of-Core Computations Using Chain Vectors,'' Proc. Euro-Par'97, Workshop on Parallel Languages, Passau, Germany, (to appear) 1997.
• M. Kandemir, J. Ramanujam, and A. Choudhary, ``A Compiler Algorithm for Optimizing Locality in Loop Nests,'' Proc. 11th Intl. Conference in Supercomputing, Vienna, Austria, July 1997.
• C. Srinilta, D. Jadav, and A. Choudhary, ``Design and Evaluation of a Data Storage and Retrieval Strategies in a Distributed Memory Continuous Media Server,'' Proc. International Parallel Processing Symposium, Geneva, Switzerland, April 1997.
• S. More, A. Choudhary, I. Foster, and M. Q. Xu, ``MTIO A Multi-Threaded Parallel I/O System,'' Proc. International Parallel Processing Symposium, Geneva, Switzerland, April 1997.
• M. Kandemir, R. Bordawekar, and A. Choudhary, ``Data Access Reorganizations in Compiling Out-of-Core Data Parallel Programs on Distributed Memory Machines,'' Proc. Intl. Parallel Processing Symposium, Geneva, Switzerland, April 1997.
• I. Foster, D. R. Kohr, Jr., R. Krishnaiyer and A. Choudhary, ``Communicating Data Parallel-Tasks: An MPI Library for Computing,'' Proc. International Conference on High Performance Computing, 1996.
• I. Foster, D. R. Kohr, Jr., R. Krishnaiyer, and A. Choudhary, ``Double Standards: Bringing Task Parallelism to HPF,'' Proc. of Supercomputing '96.
• C. Tumuluri and A. Choudhary, ``Software Latency Hiding Schemes: Evaluation of the Poststore and Prefetch Options,'' Proc. of Euro-Par '96.
• V. E. Taylor, J. Chen, M. Papka, T. Disz, R. Stevens, ``Immersive Visualization of Supercomputer Applications: Exploring the End-to-End Lag of Different Applications,'' IEEE Computational Science & Engineering, 1997, special issue on Visual Supercomputing.
• V. E. Taylor, M. Huang, T. Canfield, R. Stevens, D. Reed and S. Lamm, ``Performance Modeling of Interactive, Immersive Virtual Environments for Finite Element Simulations,'' International Journal on Supercomputer Applications and High Performance Computing, Vol. 10, No. 1, pp. 145-156, 1996.
• V. Taylor, J. Chen, T. Canfield, R. Stevens, "A Decomposition Method for Efficient Use of Distributed Supercomputers for Finite Element Application," Int. Conf. on Application Specific Systems, Arhcitectures, and Processors, 1996.
• V. Taylor, R. Stevens, K. Arnold, "Parallel Molecular Dynamics: Communication Requirements for Massively Parallel Machines," Journal of Parallel and Distributed Computing, to appear, 1997.
• Z. B. Miled, J. A. B. Fortes, R. Eigenmann, V. Taylor, ``On the Implementation of Broadcast, Scatter, and Gather in a Heterogeneous Architecture,'' Hawaii International Conference on System Sciences, to appear.
• M. Hribar, V. Taylor and D. Boyce, ``Identifying the Requirements for Decomposition of Transportation Networks,'' Proceedings of the Intel Supercomputer User's Group Conference, June 1997.
• J. Chen and V. Taylor, ``PART: A Partitioning Tool for Efficient Use of Distributed Systems,'' Proceedings of the International Conference on Applications-specific Systems, Architectures and Processors, July 14-16, 1997.
• Z. B. Miled, J. A. B. Fortes, R. Eigenmann, V. Taylor, ``A Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous Machines for Compiler and Hand-Parallelized Applications,'' IEEE Symposium on Parallel and Distributed Processing, to appear.
• Z. B. Miled, J. A. B. Fortes, R. Eigenmann, V. Taylor, ``Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach,'' Proceedings of the 30th Simulation Symposium, April 1997.
• Z. Ben Miled, R. Eigenmann, J. A. B. Fortes and V. E. Taylor, ``Hierarchical Processors-and-Memory Architecture for High Performance Computing,'' Proceedings of the Symposium on the Frontiers of Massively Parallel Computation, October 1996.
• M. Kandaswamy, V. Taylor, R. Eigenmann, J. Fortes, ``Implicit Finite Element Applications: A Case for Matching the Number of Processors to the Dynamics of the Program Execution,'' Proceedings of the SIAM Conference on Parallel Processing for Scientific Computing, 1997.
• T. Canfield, D. Diachin, T. Disz, L. Freitag, D. Heath, J. Herzog, J. Ku, M. Papka, M. Szymanski, M. Huang, J. Chen and V. Taylor, ``Visualizing Engineering Applications in the CAVE,'' Proceedings of the Virtual Reality Systems Symposium, October 1996.
• M. Kandaswamy, Z. Ben Miled, B. Armstrong, S. Kim, V. Taylor, R. Eigenmann, and J. Fortes, ``Progress Towards the Design of a Hierarchical Processors-and-Memory Architecture for High Performance,'' Petaflops Workshop at the Frontiers Conference, October 1996.
• M. Hribar, V. E. Taylor D. E. Boyce, ``Reducing the Idle Time of Parallel Transportation Applications,'' submitted to Journal on Parallel and Distributed Computing, second round of reviews.
• V. E. Taylor, B. K. Holmer, E. Schwabe and M. Hribar, ``Balancing Load versus Decreasing Communication: Parameterizing the Tradeoffs,'' submitted to Journal on Parallel and Distributed Computering, second round of reviews.
• J. Chen, V. E. Taylor, and M. Rabb, ``Bridge: A Retargetable Extensive Profiling Tool,'' submitted to IEEE Micro, January 1996.