In the same DARPA grant outlined earlier entitled, "VLSI CAD on Scalable High-Performance Computing Platforms", he has issued a subcontract to LSI Logic Corporation (contact: Dr. Sungho Kim) for transferring the technology of parallel algorithms for cell placement to that company. Last year, the project was completed. A parallel cell placement tool based on simulated annealing is now a commercial product called CME-PLACE at LSI Logic. This tool is based upon many years of research results in parallel simulated annealing developed by Prof. Banerjee and his students with some extensions.