On-Chip Network Thermal Optimization
Designed thermal-aware adaptive and deterministic routing schemes to reduce the operating temperature of on-chip routers. Developed power and thermal models of the on-chip network for chip multiprocessors (CMPs). Used the on-chip thermal profile to direct routing decisions. Minimized the activities of the hot routers by applying thermal-aware O1TURN, minimal and non-minimal routing.
Parallel Program Phase Detection
Studied the phase behavior of parallel programs running on CMPs. Analyzed the impact of on-chip network traffic on phase detection. Phase detection for parallel programs with traditional methods such as code signature and architecture metrics generated high error rate. Our scheme combined the traditional instruction based phase detection method and communication patterns of the parallel program to extract phases. With the consideration of communication information, the error rate is reduced from 11.01% to 3.41%.
Power-Efficient DRAM Architecture
Designed a DRAM architecture that reduces power consumption in the activate state without hurting performance. Introduced a page hit aware write buffer between memory controller and DRAM system. Improved page hit rate by buffering write operations intelligently to reduce DRAM power consumption. Saved DRAM power consumption by 9.6% on average.
Automated Task Distribution in Multicore Network Processors
Exploited the modularity of networking applications. Explored pipelined execution of such applications in multicore network processors. Designed an automatic method to uniformly distribute the tasks over the cores. Automated task distribution in multicore network processors is achieved via statistical analysis of packet processing time.
