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Wissner-Slivka Assistant Professor in Computer Science Department of
Electrical Eng. and Computer Science Also affiliated with Center for Ultra Scale Computing and
Information Security (CUCIS)
and Computational Biology and Bioinformatics Program (CBB) |
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Office: Tech Building, L475 (map to office) Dept. of EECS Evanston, IL 60208-3118 Fax: (847) 467-4144 Lab: Tech Building, L458 Phone: (847) 467-4610 Assistant: Julianne Flowers Phone: 847-491-7132 flowers@eecs.northwestern.edu |
Research Interest:
Computer Architecture/Microarchitecture
My research is on holistic computer architectures. Specifically,
my group works on understanding the effects of applications, users, and
underlying technologies on architectures and vice versa. These efforts include incorporating holistic effects into
architecture design process (for example, investigating the impact of
architectures on users, utilizing biological information to make
architectural decisions, estimating profitability of a design);
application-specific processors (for example, architectures and compilers for
networking, security, and data mining); and physical-aware architectures
(architectures for minimizing the power consumption, reducing operating
temperatures, and mitigating the effects of process variations). Selected Recent
Publications
- Firefly:
Illuminating Future Network-on-Chip with Nanophotonics (ISCA09) - Power to the
People: Leveraging Human Physiological Traits to Control Microprocessor
Frequency (MICRO08) - Evaluating the
Effects of Cache Redundancy on Profit (MICRO08) - Learning and
Leveraging the Relationship between Architecture-Level Measurements and
Individual User Satisfaction (ISCA08) - Efficient System
Design Space Exploration Using Machine Learning Techniques (DAC08) - A Power and
Temperature Aware DRAM Architecture (DAC08) - PICSEL:
Measuring User-Perceived Performance to Control Dynamic Frequency Scaling (ASPLOS08) - Variable Latency Caches for Nanoscale Processor
(SC07) [Winner of best
student paper award]
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Microarchitectures for Managing Chip Revenues under Process Variations (CAL07) - Yield-Aware
Cache Architectures (MICRO06) - MineBench: A
Benchmark Suite for Data Mining Workloads (IISWC06) - Thermal
Management of On-Chip Caches Through Power Density Minimization (MICRO05) - Tornado Warning:
the Perils of Selective Replay in Multithreaded Processors (ICS05) - Engineering
Over-Clocking: Reliability-Performance Trade-Offs for High-Perf. Register
Files (DSN05) - A Case for
Clumsy Packet Processors (MICRO04) Graduate Students
Advised/Co-advised
Abhishek Das*,
PhD Prabhat Kumar*,
PhD Serkan Ozdemir,
PhD Berkin
Ozisikyilmaz*, PhD Benjamin
Scholbrock, MS/PhD Alex Shye,
PhD Pan Yan,
PhD Zhuan Ye, PhD Yu Zhang,
PhD *co-advised with Prof. Choudhary Alumni
PhDArindam
Mallik, 2008 Thesis Title:
Holistic Computer Architectures based on Application, User, and Process
Characteristics (pdf) Position: Research
Scientist at IMEC MS- Matthew Erler (co-advised with Prof. Ismail), 2007. Thesis Title: TAP
Cache: Temperature-Aware Placement for Caches. - David Nguyen, 2005 Thesis Title:
Reconfigurable Architectures For Network Intrusion Detection Current Course
Spring 2009: EECS 452
- Advanced Computer Architecture - I |
