Lab 1 (Due 10/25/05):

Design a 32-bit ALU.   It will be part of a single-cycle processor and will handle a small portion of the MIPS instruction set.
This portion of the MIPS instruction set is:

arithmetic: add, sub
logical: and, or, sll
conditional: slt

Details about these instructions can be found in the back of your text and also on the included CDs.
You're allowed to use the 1-bit adder from the previous tutorial or the one in the Mentor Graphics Library.
Please use the basic building blocks provided by the Mentor Graphics Library (i.e. multiplexors, and gates, etc.).

NOTE: You must have the following input/output signals in your ALU:

Input: Operand A (32 bits), Operand B (32 bits), Control signals (at least 3 bits)
Output: Carryout, Overflow, Zero, Result (32 bits)

THINGS TO TURN IN:

1) A list of opcodes for each instruction
2) Schematic of 1 bit unit of ALU.
3) A Quicksim trace of 1 bit unit.
4) The schematic of all 32 bits (appropriately connected of course).
5) A convincing trace (0+0 isn't convincing) of all 32 bits working in sweet harmony. This trace should at least cover each instruction. We only need the traces for input and output signals. Please do not include intermediate signals.

If you should so choose to do your lab in VHDL, please turn in your well-annotated code in lieu of the schematics.

All of the above are due at the beginning of class.   Note that this is an individual assignment; each student should turn in his/her original work.

Should you have any questions feel free to e-mail your TAs.