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Patent Disclosures

  1. Y. I. Ismail, E. G. Friedman, and J. L. Neves "Driving Inductive Interconnect Using Cascaded Buffers," IBM, (patent pending).
  2. Y. I. Ismail and E. G. Friedman, "DDT: Direct Transfer Function Truncation. An Alternative to Moment Matching Techniques," University of Rochester, (patent pending).
  3. Y. I. Ismail, " Effcient Model Order Reduction via Multipoint Moment Matching," Northwestern University, (patent pending).
Publications:

Book

  1. Y. I. Ismail and E. G. Friedman "On-Chip Inductance in High Speed Integrated Circuits" Kluwer Academic Publishers, Massachusetts, 2001.


Refereed Journal Publications

  1. Y. I. Ismail and Y. Massoud, "On-Chip Inductance in High Speed Integrated Circuits",  Circuits and Devices Magazine (invited Paper).
  2. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (accepted, in press).
  3. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater Insertion in Tree Structured Inductive Interconnect," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (accepted, in press).
  4. Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," IEEE Transactions on Very Large Scale Integration

  5.      (VLSI) Systems, Vol. 8, No. 2, pp. 195 - 206, April 2000.
  6. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore Delay for RLC Trees," IEEE Transactions on Computer-Aided Design, Vol. 19, No. 1, pp. 83-97, January 2000.
  7. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance," IEEE Transactions on Very Large Scale Integration (VLSI)

  8.      Systems, Vol. 7, No. 4, pp. 442 - 449, December 1999.
  9. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines," IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications, Vol. CAS-46, No. 8, pp. 950 - 961, August 1999.
Submitted Journal Papers
  1. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Inductance Effects in RLC Trees," IEEE Transactions on Circuits and Systems 1: Fundamental Theory and Applications (in submission).
  2. Y. I. Ismail and E. G. Friedman "On the Extraction of On-Chip Inductance," IEEE Transactions on Computer-Aided Design (in submission).
  3. Y. I. Ismail and E. G. Friedman "DDT: Direct Derivation of Transfer Function. An Alternative to Moment Matching for Tree Structured Interconnect," IEEE Transactions on Computer-Aided Design (in submission).
Refereed Conference Publications
  1. M. H. Masud, S. Hsien, and Y. I. Ismail, "Circuit and Physical Level Challenges in SoC Circuits", IEEE World Multi-Conference on Systemics, Cybernetics and Informatics, (invited paper, in press).
  2. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," IEEE Workshop on Signal Processing Systems, pp. 642-652, October 2000.
  3. Y. I. Ismail and E. G. Friedman, "Fast and Accurate Simulation of Tree Structured Interconnect", IEEE Midwest Symposium on Circuits and Systems, August 2000.
  4. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," IEEE Midwest Symposium on Circuits and Systems, August 2000.
  5. Y. I. Ismail and E. G. Friedman "Sensitivity of Interconnect Delay to On-Chip Inductance," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 403-407,  May 2000.
  6. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater Insertion in Tree Structured Inductive Interconnect," Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 420-424, November 1999.
  7. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Optimizing RLC Tree Delays by Employing Repeater Insertion," Proceedings of the IEEE ASIC Conference, pp. 14-18, September 1999.
  8. Y. I. Ismail, E. G. Friedman, and Jose L. Neves, "Equivalent Elmore Delay for RLC Trees," Proceedings of the ACM/IEEE Design Automation Conference, pp. 715-720, June 1999.
  9. Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," Proceedings of the ACM/IEEE Design Automation Conference, pp. 721-724, June 1999.
  10. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Signal Waveform Characterization in RLC Trees," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 190-193, May 1999.
  11. Y. I. Ismail and E. G. Friedman, "Repeater Insertion in RLC Lines for Minimum Propagation Delay," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 404-407, May 1999.
  12. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Inductance Effects in RLC Trees," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 56-59, March 1999.
  13. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Transient Power in CMOS Gates Driving LC Transmission Lines," Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 377- 383, September 1998.
  14. Y. I. Ismail and E. G. Friedman, "Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect," Proceedings of the IEEE ASIC Conference, pp. 369-373,September 1998.
  15. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Power dissipated by CMOS Gates Driving Lossless Transmission Lines," Proceedingsof the IEEE International Symposium on Low-Power Electronics and Design, pp. 139-141, August 1998.
  16. Y. I. Ismail, E. G. Friedman, and Jose L. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance," Proceedings of the IEEE/ACM Design Automation Conference, pp. 560-565, June 1998.
  17. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Performance Criteria for Evaluating the Importance of On-Chip Inductance," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 244-247, May 1998.
  18. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 39-44, February 1998.
     
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