ECE 303 Advanced Logic Design

Time & Place

TTh 400-520pm          TCH LR5

Instructor

Prof. Hai Zhou
haizhou@ece.nwu.edu
L461 Tech Institute
(847) 491-4155
Office Hours: T 10-1130    TH 1030-12

TA

Shizhong Mei       meisz@ece.nwu.edu
Office Hours: MW 10-1130   M316

Students

Course newsgroup:    nwu.school.meas.class.ece-303

Overview

CATALOG DESCRIPTION: Overview of digital design; two level minimization and implementation using PLAs/PALs; combinational logic implementation technologies; delays, timing and hazards in digital logic; multilevel logic synthesis; CAD tools for logic minimization and synthesis; arithmetic logic circuits such as adders, multipliers; memory elements and clocking; registers, counters, shifters; random access memory and read only memory; sequential logic design; finite state machine optimization and state assignment; introduction to VHDL; VHDL structural modeling; VHDL behavioral modeling; case studies in VHDL.

Prerequisites

ECE 203

Text

  • R. H. Katz, Contemporary Logic Design. The Benjamin/Cummings Publishing Company, Inc. 1994.
  • A. Dewey, Analysis and Design of Digital Systems with VHDL. PWS Publishing, 1997.

    • Policy

    Grades: 25% Homework     25% Labs     20% Midterm      30% Final
    Late: -10% per day

    Reading materials

    0. EWD340: The humble programmer Pondering about programming--the central task of computing science--Dijkstra urges us "to approach the task with a full appreciation of its tremendous difficulty, ..., stick to modest and elegant programming languages, ..., respect the intrinsic limitations of the human mind and approach the task as Very Humble Programmers." Even though we approach hardware design instead of programming, we must prepare us with the same humble minds.

    Lecture schedule (ppt files adapted from Prof. Banerjee are given for your reference)

  • Week 1 (4/1-5): Introduction to logic design: class administration, digital design methodology, introduction to Mentor Graphics tools, review of Boolean algebra and two level minimization: logic gates, Boolean algebra review. (READINGS Katz 1.3, 1.4, 2.1, Dewey 1.3, 1.4, 4.2)  Lec01.ppt
  • Week 2 (4/8-12): Two level logic minimization: Boolean algebra, Karnaugh maps, Quine McCluskey Method, CAD tools for two level minimization, ESPRESSO algorithm. (READINGS Katz 2.2, 2.3, 2.4.1, 2.4.2 Dewey 4.3, 4.4, 4.5, 5.2, 5.3, 5.4, 5.5, 5.6, 5.7, 6.2)   Lec02.ppt  Lec03.ppt
  • Week 3 (4/15-19): Combinational logic implementation technologies: programmable logic arrays, MOS transistor logic, multiplexers, decoders, ROMS. (READINGS Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, Dewey 5.7)  Lec04.ppt
  • Week 4 (4/22-26): Multilevel logic synthesis: Mapping 2-level logic to NANDs and NORs, CAD tools for multilevel logic. (READINGS Katz 3.1, 3.2) Lec05.ppt
  • Week 5 (4/29-5/3): Arithmetic Logic Circuits: review of number systems, Adders, ripple carry, carry lookahead, carry select adders, combinational array multipliers, ALUs, general function units. (READINGS Katz 5.2.1, 5.2.2, 5.2.4, 5.3, 5.5, 4.6)   Lec06.ppt
  • 5/7: Midterm exam.  sample exercises
  • Week 6 (5/9): Delays and timing in multilevel logic: gate delays, timing waveforms, static/dynamic hazards and glitches, designs to avoid hazards. (READINGS Katz3.3, 3.4, 3.5.2, Dewey 6.5.1, 6.5.2)  Lec07.ppt
  • Week 7 (5/13-17): Memory elements and clocking: latches, flip-flops, timing issues, setup and hold times, registers, counters. (READINGS Katz  6.1, 6.2, 7.1, 7.2, 7.4, 7.5, 7.6, Dewey 10.2, 10.3, 10.4)  Lec08.ppt   Lec09.ppt
  • Week 8 (5/20-24): Finite State Machine Design: Review of state machine design, Moore/Mealy machine, finte state machine word problems. Finite State Machine Optimization: state minimization algorithms, row matching method, implicict chart method, paper and pencil methods for state assignment, one-hot encodings. (READINGS Katz 8.1, 8.2, 8.4, 8.5, 9.1, 9.2.1, 9.2.2, 9.3, Dewey 9.1, 9.2, 9.3)   Lec10.ppt  Lec11.ppt
  • Week 9 (5/27-31): Introduction to VHDL: VHDL language basics, interface, architecture body, behavioral VHDL, process statements, delay models. VHDL Structural Modeling: Review of VHDL, structural VHDL modeling, use of hierarchy, combinational designs, component instantiation, concurrent statments, test benches. (READINGS Dewey 11.2-11.6, 15.1, 15.2, 18.2-18.5, 12.1-12.4, 13.1-13.8)  Lec12.ppt     Lec13.ppt
  • Week 10 (6/3-7): VHDL Modeling of Sequential Machines: Describing sequential behavior in VHDL, latches, flip flops, FSMs, Synthesis using VHDL, packages in VHDL. Course Review. (READINGS Dewey 17.1-17.10, 18.1, 18.2)  Lec14.ppt
  • Sample final exam     *correct solution to problem 3*

    • Labs (due before the class on each date)

    1. (due 4/16) Introduction to the use of the Mentor Graphics tools--Design Architect schematic entry system, the Quicksim logic simulator.  LAB1 word file     LAB1 ps file
    2. (due 4/25) Use of the Mentor Graphics Tools to design a 4-bit ripple carry adder, learn to design combinational logic, simulations with delays. LAB2 pdf file
    3. (due 5/9) Two-level and multiple-level logic optimization using Espresso and SIS. LAB3 pdf file   SIS paper(just for reference, not needed)
    4. (due 5/28) Design of an 8-state finite state machine using the Mentor Graphics tools, use of manual state assignment, use of D flip-flops, and combinational gates.   LAB4 pdf file
    5. (due 6/6) Use of VHDL in the Mentor Graphics tools, design of 8-bit finite state machine using behavioral and structural VHDL, VHDL simulation.  LAB5 pdf file     checker.vhd   (More hints: use case and if statements for the diagram design (see page 14 in Lec14); use guarded signal assignment for the FF design (see page 11 in Lec14)--guarding Z1 and Z2 will make their waveforms more stable.)

    Homework (due before the class on each date)

    1. (due 4/18)Two level minimization and implementation  hw1.ps
    2. (due 5/2) Multilevel minimization and implementation  hw2.ps
    3. (due 5/21) Timing, hazards, and sequential circuit basics hw3.ps
    4. (due 6/4) Finite state machine design, state optimization hw4.ps

    Reminder

    Please check back often to this page (www.ece.nwu.edu/~haizhou/ece303.html) for updates and course material download.