An Automated and Power-Aware Framework for Utilization of IP Cores in
Hardware Generated from C Descriptions
Alex Jones and Prith Banerjee
Abstract
Use of hand optimized Intellectual Property (IP) logic cores is prolific
in hardware design. These IP cores range from rather complicated signal
processing transforms and filters to arithmetic operators. While IP cores
remain a standard way to utilize the improvement in chip fabrication
technology and contend with time to market pressure through reuse,
popularity of tools generating hardware descriptions from high level
languages is increasing in popularity. PACT HDL attempts to combine these
two methods within a power-aware framework. The PACT HDL compiler
generates power optimized VHDL/Verilog from a C language description. The
work presented here describes an automated framework to incorporate
arbitrary IP logic cores corresponding to C intrinsic operators. The logic
cores to be used may be specified by the user through compiler directives
or compiler command line options. The framework is power-aware through
using a clock-gating technique to turn off the IP cores when not in use.
The validity of the approach is demonstrated using several image and
signal processing benchmarks.
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