PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and
Performance Optimizations
Alex Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang,
Alok Choudhary, and Prith Banerjee
Abstract
Chip fabrication technology continues to plunge deeper into sub-micron
levels requiring hardware designers to utilize ever-increasing amounts
logic and shorten design time. Toward that end, high-level languages such
as C/C++ are becoming popular for hardware description and synthesis in
order to more quickly leverage complex algorithms. Similarly, as logic
density increases due to technology, power dissipation becomes an
increasing important metric of hardware design. PACT HDL, a C to HDL
compiler, merges automated hardware synthesis of high-level algorithms
with power and performance optimizations and targets arbitrary hardware
architectures, particularly in a System on a Chip (SoC) setting that
incorporates reprogrammable and application-specific hardware. PACT HDL is
intended for applications well suited to custom hardware implementation
such as image and signal processing codes. By making the compiler modular
and flexible, optimizations may be executed in any order and at different
levels in the compilation process. PACT HDL generates industry standard
HDL codes, such as RTL Verilog and VHDL, which may be synthesized and
profiled for power using commercial tools. Optimizations such as
functional unit pipelining and reverse code levelization focus on reducing
power consumed by the design without sacrificing performance.