A Hardware Testbed for Distributed Heterogeneous Adaptive Computing

Christopher Bachmann

Abstract

Adaptive computing systems are composed of reconfigurable hardware elements that are capable of adapting to various computation requirements. Using these reconfigurable hardware elements, adaptive computing systems provide significant performance improvements over conventional non-reconfigurable systems. However, completely reconfigurable systems, such as those based entirely around FPGAs, become very unsuitable for implementing complex applications. This is due to both the time to develop algorithms and then implement them, as well as the FPGAs being slower than processor's internal computational units when implementing the same functions. The solution, being developed by the MATCH project, is to merge various commercial-off-the-shelf (COTS) components into one cohesive unit. Such components would include not only FPGAs, but DSPs and embedded processing elements as well. This allows the advantages of each element to be combined, such as the ability of the FPGAs to deal with more custom processing. The primary goal of the MATCH project is to explore methods for bridging the gap between the high level of applications developers, and the low level control required by the adaptive computing environment. This would include new developments in compiler technologies to take advantage of such a heterogeneous environment. In order to test the new theories and ideas of the MATCH system developers a testbed was developed including the necessary custom components targeted by the MATCH system developers. The actual testbed itself consists of a Motorola embededded board, an Annapolis Microsystems WILDCHILD, a Transtech DSP board, and a Force 5V Sparc based board. This thesis will present prior work that has been done in the area of adaptive computing, the testbed that we have developed, and the results of various benchmarks on the testbed, including matrix multiply on the various components.

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