Interconnect power dissipation is becoming a major component of power consumption in a circuit especially in sub-micron technologies. The energy dissipated by a particular interconnection link is determined by the switching activity on that link and also on its capacitance. The switching activity is determined by the schedule and binding, whereas the capacitance is determined by the floorplan. Scheduling, binding and floorplanning are closely inter-related.

A simultaneous scheduling, binding and floorplanning algorithm is presented which attempts to minimize interconnect energy dissipation. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower power, latency and area. We show that it is possible to reduce the interconnect energy dissipation by upto 60 percent for high-level synthesis benchmark circuits.

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