Parallel Test Generation

Key Contributors

Research Papers

A Parallel Algorithm for Fault Simulation Based on PROOFS (52K)
Steven Parkes, Prithviraj Banerjee, and Janak H. Patel
in Proceedings of the 1995 International Conference on Computer Design, Austin, TX, October 1995

ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation (56K)
Steven Parkes, Prithviraj Banerjee, and Janak H. Patel
in Proceedings of the 1994 Design Automation Conference, San Diego, CA, June 1994

Portable Parallel Test Generation for Sequential Circuits
Balkrishna Ramkumar and Prithviraj Banerjee (51K)
in Digest of Papers, 1992 International Conference on Computer-Aided Design, Santa Clara, CA, November 1992

Performance Trade-offs in a Parallel Test Generation / Fault Simulation Environment (107K)
Srinivas Patil and Prithviraj Banerjee
in IEEE Transactions on Computer Aided Design, December 1991

Parallel Test Generation for Sequential Circuits on General Purpose Multiprocessors
Srinivas Patil, Prithviraj Banerjee, and Janak H. Patel
in Proceedings of the 1991 Design Automation Conference, San Francisco, CA, June 1991

Parallel Algorithms for Test Generation and Fault Simulation (296K)
Srinivas Patil
PhD dissertation, Department of Electrical Engineering, University of Illinois, August 1990, Technical Report CRHC-90-12/UILU-ENG-90-2245

A Parallel Branch and Bound Algorithm for Test Generation (69K)
Srinivas Patil and Prithviraj Banerjee
in IEEE Transactions on Computer Aided Design, March 1990

Fault Partitioning Issues in an Integrated Parallel Test Generation Fault Simulation Environment
Srinivas Patil and Prithviraj Banerjee
in Proceedings of the 1989 International Test Conference, Washington, DC, August 1989

A Parallel Branch and Bound Approach to Test Generation (41K)
Srinivas Patil and Prithviraj Banerjee
in Proceedings of the 1989 Design Automation Conference, Las Vegas, NV, June 1989

send any questions to banerjee@ece.nwu.edu