Parallel Synthesis for VLSI Design

Key Contributors

Research Papers

Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
Pradeep Prabhakaran and Prithviraj Banerjee
to appear in Proceedings of the 1996 International Conference on Computer Design, Austin, TX, October 1996

A Parallel Algorithm for State Assignment in Finite State Machines (111K)
Gagan Hasteer and Prithviraj Banerjee
to appear in Proceedings of the 1996 International Conference on Parallel Processing, Bloomingdale, IL, August 1996

Parallel Algorithms for Algebraic Factorization in Logic Synthesis (176K)
Sumit Roy
MS thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 1996, Technical Report CRHC-96-07/UILU-ENG-96-22??

Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs (88K)
Pradeep Prabhakaran and Prithviraj Banerjee
Technical Report CRHC-96-05/UILU-ENG-96-2209, March 1996, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL

Parallel Algorithms for State Assignment of Finite State Machines (219K)
Gagan Hasteer
MS thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, January 1996, Technical Report CRHC-96-02/UILU-ENG-96-2202

Parallel Algorithms for Logic Synthesis Using the MIS Approach (80K)
Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of the 1995 International Parallel Processing Symposium, Santa Barbara, CA, April 1995

Parallel Logic Synthesis Using Partitioning (70K)
Kaushik De and Prithviraj Banerjee
in Proceedings of the 1994 International Conference on Parallel Processing, St. Charles, IL, August 1994

A Portable Parallel Algorithm for Logic Synthesis using Transduction (133K)
Kaushik De, Balkrishna Ramkumar, and Prithviraj Banerjee
in IEEE Transactions on Computer Aided Design, May 1994

Parallel Algorithms for Logic Synthesis (370K)
Kaushik De
PhD dissertation, Department of Electrical Engineering, University of Illinois, September 1993, Technical Report CRHC-93-20/UILU-ENG-93-2235

A Shared Memory Parallel Algorithm for Logic Synthesis (63K)
Chieng-Fai Lim, Kaushik De, Prithviraj Banerjee, and Saburo Muroga
in Proceedings of the 1993 International VLSI Design Conference, Bombay, India, January 1993

ProperSYN: A Portable Parallel Algorithm for Logic Synthesis (61K)
Kaushik De, Balkrishna Ramkumar, and Prithviraj Banerjee
in Digest of Papers, 1992 International Conference on Computer-Aided Design, Santa Clara, CA, November 1992

A Parallel Algorithm for Multi-level Logic Synthesis Using the Transduction Method (129K)
Chieng-Fai Lim
MS thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, September 1991, Technical Report CRHC-91-27

A Parallel Algorithm for Algebraic Factoring with Applications to Multilevel Logic Minimization
Gary Gene Zipfel
MS thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, June 1991, Technical Report CRHC-91-24
send any questions to banerjee@ece.nwu.edu