PANTHER PROJECT PUBLICATIONS (1997-98)
-
M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, J. Ramanujam,
``A Linear Algebra Framework for Automatic Determination of Optimal
Data Layouts,''
To appear in {\em IEEE Transactions on Parallel and Distributed Systems},
1998.
-
D. Krishnaswamy and P. Banerjee,
``Exploiting Task and Data Parallelism in Parallel Hough and Radon
Transforms,''
{\em Proc. Int. Conference on Parallel Processing (ICPP-97)},
Bloomingdale, IL, Aug. 1997.
-
V. Krishnaswamy, G. Hasteer, and P. Banerjee,
``Load Balancing and Workload Minimization of Overlapping Parallel Tasks,''
{\em Proc. Int. Conference on Parallel Processing (ICPP-97)},
Bloomingdale, IL, Aug. 1997.
-
J. A. Chandy and P. Banerjee, ``A Parallel Circuit-Partitioned Algorithm for Timing-driven Standard Cell Placement,''
{\em Proc. Int. Conference on Computer-Design (ICCD-97)}, October 1997, Austin, TX.
-
G. Hasteer, A. Mathur, and P. Banerjee, ``A Framework for Equivalence
Checking of Multi-Phase FSMs,''
{\em Proc. International High-Level Design Validation and Test Workshop},
Oakland, CA, Nov. 1997.
-
P. Prabhakaran and P. Banerjee, ``Simultaneous Scheduling, Binding and
Floorplanning in High-Level Synthesis,'' {\em Proc. 11th
International Conference on VLSI Design (VLSI Design'98)}, Chennai,
India, Jan. 1998.
-
S. Roy, P. Banerjee and M. Sarrafzadeh, ``Partitioning Sequential
Circuits for Low Power,'' {\em Proc. 11th International
Conference on VLSI Design (VLSI Design'98)}, Chennai, India, Jan. 1998.
-
S. Roy, A. Harm, and P. Banerjee, ``PowerShake: A Low Power Driven
Clustering and Factoring Methodology for Boolean Expressions,''
{\em Proc. Design, Automation and Test in Europe Conference
(DATE 98)}, Paris, France, Feb. 1998.
-
D. Chakrabarti, A. Lain, and P. Banerjee,
``Evaluation of Compiler and Runtime Library Approaches for Supporting
Parallel Regular Applications,''
{\em Proc. Int. Parallel
Processing Symp. (IPPS-98)}, Apr. 1998, Orlando, FL.
-
M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, N. Shenoy,
``A Generalized Framework for Global Communication Optimization,''
{\em Proc. Int. Parallel Processing Symp. (IPPS-98)}, Apr. 1998,
Orlando, FL.
-
Z. Xing and P. Banerjee, ``A Parallel Algorithm for Zero Skew Clock Tree Routing,''
{\em Proc. Int. Symp. Physical Design (ISPD98)},
Apr. 1998, Monterey, CA.
-
S. Roy and P. Banerjee, ``Resynthesis of
Sequential Circuits for Low Power,''
{\em Proc. International
Conference on Circuits and Systems (ISCAS-98)},
Monterey, CA, May 1998.
-
P. Prabhakaran and P. Banerjee,
``Parallel Algorithms for Scheduling, Binding, and Floorplanning
in High -Level Synthesis,''
{\em Proc. International Conference on Circuits and Systems (ISCAS-98)},
Monterey, CA, May 1998.
-
G. Hasteer, A. Mathur, and P. Banerjee,
``An Implicit Algorithm for Finding Steady States and its Application
to FSM Verification,''
{\em Proc. Design Automation Conference (DAC-98)},
Jun. 1998, San Francisco, CA.
-
V. Kim and P. Banerjee,
``Parallel Algorithms for Power Estimation,''
{\em Proc. Design Automation Conference (DAC-98)},
Jun. 1998, San Francisco, CA.
-
M. Wang, M. Sarrafzadeh, and P. Banerjee,
``Placement with Incomplete Data,''
{\em Proc. Design Automation Conference (DAC-98)},
Jun. 1998, San Francisco, CA.
-
V. Krishnaswamy and P. Banerjee,
``Parallel Compiled Event Driven VHDL Simulation,''
{\em Proc. Int. Conf. Supercomputing (ICS-98)}, Melbourne, AUSTRALIA,
July 1998.
-
D. R. Chakrabarti, N. Shenoy, A. Choudhary, and P. Banerjee,
``An Efficient Uniform Run-time Scheme for Mixed Regular-Irregular Applications,''
{\em Proc. Int. Conf. Supercomputing (ICS-98)}, Melbourne, AUSTRALIA,
July 1998.
-
M. Kandemir, A. Choudhary, N. Shenoy, and P. Banerjee,
``A Hyperplane Based Approach for Optimizing Spatial Locality
in Loop Nests,''
{\em Proc. Int. Conf. Supercomputing (ICS-98)}, Melbourne, AUSTRALIA,
July 1998.
-
M. Kandemir, N. Shenoy, P. Banerjee, J. Ramanujam, and
A. Choudhary,
``Minimizing Data and Synchronization Costs in One-Way Communication,''
{\em Proc. Int. Conf. Parallel Processing (ICPP98)},
Minneapolis, MN, Aug. 1998.
-
Z. Xing and P. Banerjee,
``A Parallel Algorithm for Timing-Driven Global Routing for Standard Cells,''
{\em proc. Int. Conf. Parallel Processing (ICPP98)},
Minneapolis, MN, Aug. 1998.
-
M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, and P. Banerjee,
``Enhancing Spatial Locality using Data Layout Optimizations,''
{\em Proc. European Conference on Parallel Processing (Euro-Par'98),}
Southampton, ENGLAND, Sep. 1998.
-
S. Roy, A. Harms and P. Banerjee,
``A Low Power Logic Optimization Methodology Based on a Fast Power Driven Mapping,''
{\em Proc. Int. Conf. Computer Design (ICCD-98)}, Oct. 1998.
-
V. Krishnaswamy, G. Hasteer, and P. Banerjee,
``Automatic Parallelization of Compiled Event Driven VHDL
Simulation,''
submitted to {\em IEEE Transactions on CAD}, April 1997,
revised April 1998.
-
D. Chakrabarti, N. Shenoy, A. Lain, A. Choudhary, P. Banerjee,
``An Efficient Uniform Compilation Scheme for Parallelizing Mized
Regular-Irregular Applications,''
submitted to {\em IEEE Transactions on Parallel and Distributed Systems.}
-
D. Krishnaswamy, E. Rudnick, P. Banerjee, J. H. Patel,
``SPITFIRE: Synchronous and Asynchronous Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation,''
submitted to {\em IEEE Transactions on CAD}, March 1998.
-
D. Krishnaswamy, M. Hsiao, E. Rudnick, P. Banerjee, J. H. Patel, V. Saxena,
``Parallel Genetic Algorithms for Sequential Circuit Test Generation,''
submitted to {\em IEEE Transactions on Computers}, March 1998.
-
M. Kandemir, N. Shenoy, P. Banerjee, J. Ramanujam, and
A. Choudhary,
``Minimizing Data and Synchronization Costs in One-Way Communication,''
submitted to {\em IEEE Trans. on Parallel and Dist. Systems},
March 1998.
-
M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, N. Shenoy,
``A Global Communication Optimization Technique Based on Data Flow Analysis
and Linear Algebra''
submitted to {\em ACM Trans. on Programming Languages and Systems (TOPLAS)},
March 1998.
-
M. Kandemir, A. Choudhary, P. Banerjee, J. Ramanujam, and N. Shenoy,
``Minimizing Data and Synchronization Costs in One-Way
Communication,,'' submitted to {\em IEEE Transactions on Parallel and
Distributed Systems}, March 1998.
-
P. Prabhakaran, J. Crenshaw, P. Banerjee, and M. Sarrafzadeh,
``Simultaneous Scheduling, Binding and Floorplanning in High-Level
Synthesis,''
submitted to {\em IEEE Transactions on CAD},
May 1998.
-
Z. Xing and P. Banerjee, ``A Parallel Algorithm for Zero Skew Clock Tree Routing,''
submitted to {\em IEEE Transactions on CAD,
(special issue on physical design)},
June 1998.
-
J. S. Chen and P. Banerjee,
``Parallel Construction Algorithms for BDDs,''
Submitted to {\em Parallel and Distributed Computing Systems (PDCS98)},
Chicago, Nov. 1998.
-
A. Mishra and P. Banerjee,
``A Fault Tolerant Multi-Grid Algorithm,''
Submitted to {\em Parallel and Distributed Computing Systems (PDCS98)},
Chicago, Nov. 1998.
-
P. Prabhakaran, J. Crenshaw, P. Banerjee, and M. Sarrafzadeh,
``Simultaneous Scheduling, Binding and Floorplanning for Interconnect
Power Optimization,'' Submitted to {\em International Symposium on Low
Power Electronics and Design}, Monterey, CA, August 1998.
-
N. Shenoy, M. Kandemir, D. Chakarabarti, A. Choudhary, P. Banerjee,
``Estimating Memory Access Costs on Distributed Shared Memory Multiprocessors,''
Submitted to {\em Symposium on Architectural Support of Programming
Languages and Operating Systems (ASPLOS-98)},
Santa Clara, CA, Oct. 1998.
-
Y. Yuan and P. Banerjee,
``A Parallel Algorithm for 3D Resistance and Capacitance Extraction
using the Boundary Element Method,''
Submitted to {\em Int. Conf. Computer Design (ICCD-98)}, Oct. 1998.
-
P. Banerjee and Y. Yuan,
``ICE: Incremental 3-Dimensional Capacitance and Resistance
Extraction for an Iterative Design Environment,'' submitted to {\em
1998 International Conference on Computer-Aided Design (ICCAD-98)},
San Jose, CA, Nov. 1998.
-
S. Roy and P. Banerjee, ``Power Drive: A fast, canonical POWER
estimator for DRIVing synthEsis,''
submitted to {\em 1998
International Conference on Computer-Aided Design (ICCAD-98)}, San
Jose, CA, Nov. 1998.
-
G. Hasteer, A. Mathur, and P. Banerjee,
``Efficient Equivalence Checking of Multi-Phase Designs Using Retiming,''
submitted to {\em 1998
International Conference on Computer-Aided Design (ICCAD-98)}, San
Jose, CA, Nov. 1998.
-
D. Chakrabarti, P. Joisha, J. Chandy, D. Krishnaswamy,
V. Krishnaswamy, and P. Banerjee, ``WADE: A Web-Based Automated
Parallel CAD Environment,'' submitted to {\em International Conference
on High Performance Computing (HiPC'98)}, India, Dec. 1998.
-
Y. Yuan and P. Banerjee, ``A Parallel 3-D Capacitance and Resistance
Extraction Program Based on BEM,'' submitted to {\em 1999 VLSI Design
Conference}, Goa, India, Jan. 1999.
-
P. Prabhakaran, J. Crenshaw, P. Banerjee, and M. Sarrafzadeh,
``Simultaneous Scheduling, Binding and Floorplanning for Interconnect
Power Optimization,'' submitted to {\em 1999 VLSI Design Conference},
Goa, India, Jan. 1999.
\begin{itemize}
- S. Goil and A. Choudhary, ``High-Performance OLAP and Data
Mining on Parallel Computers,'' Journal of Data Mining and Knowledge
Discovery, Vol 1 No.4, 391-417, 1997.
- M. Kandemir, J. Ramanujam, and A. Choudhary, ``Compiler
Algorithms for Optimizing Locality and Parallelism on Shared and
Distributed Memory Machines,''{\em Proc. International Conference on
Parallel Architectures and Compilation Techniques (PACT'97)},
pp. 236-247, San Francisco, CA, Nov. 1997.
- C. Srinilta and A. Choudhary, ``Performance Enhancement Using
Intraserver Caching in a Continuous Media Server,'' {\em
Proc. RIDE'98}, Orlando, FL, Feb. 1998.
- Jesus Carretero, Jaechun No, Sung-soon Park, Alok Choudhary, and Pang Chen
COMPASSION: A Parallel I/O Runtime System Including Chunking and Compression
for Irregular Applications, HPCN'98, Amsterdam, NL, April 1998.
- Jaechun No, Jesus Carretero, Sung-soon Park, Alok Choudhary,
and Pang Chen. ``Design and Implementation of a Parallel I/O Runtime
System for Irregular Applications,'' Proceedings of IPPS'98. March,
1998, Orlando, USA.
- Jesus Carretero and Alok Choudhary, ``Interface Specification
for the Multimedia Integrated Parallel File System (MiPFS),''
Technical Report, CPDC-TR-9802-013, Northwestern University
-
S. Hauck, S. Knol, "Data Security for Web-based CAD",
{\em Proc. Design Automation Conference}, 1998. Journal version submitted to
{\em IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems}.
-
S. Hauck, "Configuration Prefetch for Single Context Reconfigurable
Coprocessors", {Proc. ACM/SIGDA International Symposium on Field-Programmable Gate
Arrays,} pp. 65-74, 1998. Journal version submitted to {\em IEEE Transactions on
VLSI Systems}.
-
S. Hauck, M. M. Hosler, T. W. Fry, "High Performance Carry Chains for
FPGAs", {\em Proc. ACM/SIGDA International Symposium on Field-Programmable Gate
Arrays}, pp. 223-233, 1998. Journal version submitted to IEEE Transactions
on VLSI Systems.
-
S. Hauck, Z. Li, E. J. Schwabe, "Configuration Compression for the
Xilinx XC6200 FPGA", IEEE Symposium on FPGAs for Custom Computing Machines,
1998. Journal version submitted to IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems.
-
S. Hauck, Z. Li, "Don't Care Discovery for FPGA Configuration
Compression", submitted to International Conference on Computer-Aided
Design, 1998.
-
S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera
Reconfigurable Functional Unit", IEEE Symposium on FPGAs for Custom
Computing Machines, pp. 87-96, 1997.
-
G. Tellez and M. Sarrafzadeh,
``On Distance Preserving Rectlinear Steiner Trees,''
VLSI Design, Vol. 7, No. 1, April 1998.
-
Amir Farrahi and Gustavo Tellez and M. Sarrafzadeh,
``Exploiting Sleep Mode for Memeory Partitions and Other Applications,''
to appear in {\em VLSI Design}.
-
Gustavo Tellez and M. Sarrafzadeh,
``Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints,''
to appear in {\em IEEE Transactions on Computer-Aided Design}.
-
D. S. Chen and Gary Yeap and M. Sarrafzadeh,
``State Encoding of Finite State Machines for Low Power Design''
to appear in {\em VLSI Design}.
-
E.-L. Lin, C. K. Wong
and M. Sarrafzadeh,
``Floating Steiner Trees,''
{\em IEEE Transactions on Computers,} Vol. 47, No. 2, February 1998, pp. 197-211.
-
Wei-Liang Lin and M. Sarrafzadeh,
`` On the Power of Re-Synthesis,''
To appear in {\em SIAM Journal on Computing}
-
Salil Raje and M. Sarrafzadeh,
``Scheduling with Multiple Voltages''
{\em INTEGRATION: The VLSI Journal,} 23 (1997), pp. 37-59;
-
David Knol and Gustavo Tellez and M. Sarrafzadeh,
`` A Delay Budgeting Algorithm Ensuring Maximum Flexibility in Placement,''
{\em IEEE Transaction on CAD,} Vol. 16, No. 11, November 1997,
pp. 1332-1341.
-
Sara Nicoloso and M. Sarrafzadeh,
``Sum Coloring Problem on Interval Graphs'',
to appear in {\em Algorithmica}.
-
Amir Farrahi and D. T. Lee and M. Sarrafzadeh,
``Two-Way and Multi-Way Partitioning of a Set of Intervals
for Clique-Width Maximization''
to appear in {\em Algorithmica}
-
Jun-Dong Cho, and S. Raje, and M. Sarrafzadeh,
`` Fast Approximation Algorithms on Maxcut, k-coloring and k-color
Ordering for VLSI Applications'',
to appear in {\em IEEE Transactions on Computers}.
-
J. D. Cho. and M. Sarrafzadeh,
``Mixed LP and Mincost Flow-based Four-bend Globar Routing
in Two Dimensional Arrays''
to appear in {\em IEEE Transactions on CAD.}
-
D. Knol, G. Tellez and M. Sarrafzadeh,
``A Solution to Large Scale Timing-Driven Placement Problems, ''
{\em Proceedings of 1997 Design Automation Conference (DAC-97)},
June. 1997.
-
A. Farrahi and M. Sarrafzadeh,
``TDD: Fast Technology Mapping with Accurate Prediction'',
ASIC'97: Annual IEEE International ASIC Conference and Exhibit,
-
M. Enos, S. Hauck and M. Sarrafzadeh,
``Logic Partitioning with Replication'',
{\em Proc. ICCAD 97,} November, San Jose, CA.
-
M. Wang and M. Sarrafzadeh,
``NRG: Global and Detailed Placement''
{\em Proc. ICCAD 97}, November 1997, San Jose, CA.
-
J. Crenshaw and M. Sarrafzadeh,
``Low-Power Driven Scheduling and Binding ``
{\em 1997 Great Lakes SYmposium on VLSI,}
February 19-21, 1998, Lafayette, Louisiana.
-
K. Bazargan, Sam Kim, and M. Sarrafzadeh,
``Nostradamus: Floorplanner of Uncertain Designs'',
{\em Proceedings of the 1998 International Symposium on Physical Design (ISPD 98)}.
-
M. Wang, P. Banerjee, and M. Sarrafzadeh,
``Placement with Incomplete Data'',
{\em Proceedings of 1998 Design Automation Conference (DAC-98)},
June 1998.
-
E. Papadopoulou and D. T. Lee,
``Critical Area Computation -- A New Approach,''
{\em Proc. 1998 Int'l Symposium on Physical Design,} Monterey,
CA, April 1998, pp. 89-94.
-
D. T. Lee, C. F. Shen and S. M. Sheu,
``GeoSheet: A Distributed Visualization Tool for Geometric
Algorithms,''
{\em Int'l J. Comput. Geometry and Applications,} (8,2) April 1998,
pp. 119-155.
-
K. Aoki and D. T. Lee,
``Towards Web-Based Computing,''
Northwestern University ECE department Tech. Report, Feb. 1998, submitted for publication.
-
J. Shim, P. Scheuermann, and R. Vingralek,
``Proxy Cache Design: Algorithms, Implementation and Performance,''
Submitted to {\em IEEE Transactions on Knowledge and Data Engineering}.
-
M. Sayal, Y. Breitbart, P. Scheuermann, R. Vingralek,
"Selection Algorithms for Replicated Web Servers,''
{\em Proc, Workshop on Internet Server Performance (WISP98)}, May 1998.
-
Z. Ben Miled, J. A. B. Fortes, R. Eigenman and V. Taylor, {\em A
Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous
Machines for Compiler and Hand Parallelized Applications},
to appear by invitation in the {\bf International Journal of parallel and
Distributed Systems and Networks}.
-
V. E. Taylor, R. Stevens and K. Arnold,
{\em Parallel Molecular Dynamics: Implications for
Massively Parallel Machines}, {\bf Journal on Parallel and
Distributed Computing}, Vol. 45:2, September 1997, pp. 166--175.
-
M. Hribar, V. E. Taylor D. E. Boyce, {\em Reducing the Idle Time in
Parallel Shortest Path Algorithms},
to appear in {\bf Journal on Parallel and Distributed Computing},
-
V. E. Taylor, B. K. Holmer, E. Schwabe and M. Hribar,
{\em Balancing Load versus Decreasing Communication: Parameterizing
the Tradeoffs}, submitted to {\bf Journal on Parallel and Distributed
Computering}, second round of reviews.
-
Z. B. Miled, J. A. B. Fortes, R. Eigenmann, V. Taylor,
{\em On the Implementation of Broadcast, Scatter, and
Gather in a Heterogeneous Architecture},
Hawaii International Conference on System Sciences, January 1998.
-
W. Smith, I. Foster and V. Taylor, {\em Predicting Application Run
Times Using Historical Information}, 4th Workshop on Job Scheduling
Strategies for Parallel Processing (in conjunction with IPPS 1998),
April 1998.
-
J. Chen and V. Taylor, {\em PART: A Partitioning Tool for Efficient Use of
Distributed Systems}, Proceedings of the International
Conference on Applications-specific Systems, Architectures and Processors,
July 14-16, 1997.
-
M. Hribar, V. E. Taylor and D. E. Boyce, {\em Performance Study of
Parallel Shortest Path Algorithms: Characteristics of Good Decompositions},
Proceedings from ISUG Conference , June, 1997.
-
Z. B. Miled, J. A. B. Fortes, R. Eigenmann, V. Taylor,
{\em A Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous
Machines for Compiler and Hand-Parallelized Applications}, 1997 IEEE
Symposium on Parallel and Distributed Processing, October 1997.
-
J. Chen and V. Taylor, {\em Identifying Good Metrics for Mesh
Partitioning for Distributed Systems}, Domain Decomposition
Conference, 1998.
-
M. Hribar, V. Taylor and D. Boyce, "Identifying Requirements for Good
Network Decomposition Methods", INFORMS National Meeting, October 1998.
-
J. Chen and V. Taylor, {\em Decomposition of Finite Element Mesh for
Dedicated Heterogeneous Distributed Systems}, Domain Decomposition
Conference, 1997.
-
M. Hribar, V. E. Taylor and D. Boyce, {\em Parallel Transportation
Applications}, INFORMS Fall Meeting, November 1997.
-
J. Chen and V. E. Taylor, {\em Mesh Partitioning for Distributed
Systems}, High Performance Distributed Computing Conference, Chicago,
1998.