The equipment to be acquired in this project will be used
to support research and education in the following
tasks. An overview of the tasks and their interactions
are shown below.
This area will investigate methods for harnessing parallel and distributed computing resources, logic emulators, and high-speed networking to provide radically higher performance for the critical area of VLSI CAD. By leveraging the World-Wide-Web and the growth of the Network Computer model of computing, we will provide a centralize CAD computing center accessible to digital designers throughout the country. Innovative research on parallel and distributed CAD algorithms, custom-computing solutions to CAD problems, and infrastructure issues for Web-based centralized servers and interaction management will drive this new methodology in VLSI design. We will also use the Mentor Graphics VLSI CAD tools described in Task 4 in some of our research on CAD tools. The specific sub-tasks and the investigators in this task are:
This project entails design, development and implementation of techniques to perform high-performance I/O and its use in applications in a heterogeneous network environment. Specifically, the project involves the development of file system, runtime system, file management, and optimizations including collective I/O, data caching, data reuse, data sieving. Furthermore, it involves automatic determination of striping parameters, migration and load balancing for files based on the user patterns and access characteristics. Techniques for caching and management of caches for applications such as data warehousing will be developed for a network of heterogeneous workstations and parallel computers. The specific subtasks and the investigators in this task are:
This project will explore an efficient parallel programming environment for network of heterogeneous systems including workstations, PCs and parallel machines. The project will involve development of compilation optimizations for regular and irregular data structures, automatic decomposition of data and tasks, support for out-of-core computations and hierarchical memories. The set of tools entails domain decomposition, scheduling, efficient interprocessor (and inter-machine) communication and performance monitoring and visualization. These tools will be developed for computations within a local distributed systems as well as across geographically distributed high-performance computers. The specific subtasks and the investigators in this task include:
The combination of the formation of the new ECE Department and the hiring of two new faculty has provided impetus for a major revision to the Computer Engineering Curriculum. Significant revisions have been made to the undergraduate and graduate curricula. The revisions entail the addition of new capstone design courses, new parallel and distributed computing courses, and the addition of strong laboratory components to existing courses. All of the design courses in the area of digital design, computer architecture and VLSI will be based upon one suite of design tools, the Mentor Graphics tools, for which negotiations are underway to get 20 site licenses. The new curriculum will require many new high-performance workstations, for which the proposed infrastructure is essential. In addition, the parallel and distributed computing courses will require the network of workstations to provide the necessary platforms for teaching the concepts. Of the total proposed workstations a subset of them (about 13 machines) will be used in a shared research and education mode in a centralized facility in the workstation lab. In this project, we will explore new instructional techniques that take advantage of the high bandwidth and high speed. We will be using Web-based learning in these courses. All the faculty listed in this project will participate in this task. We will also involve undergraduate students in research using these equipments.
Each of the tasks in this project has strong
synergy with the other tasks.
While each of the investigators was doing research in
many of these topics individually,
the researchers are coming together
to perform some strong, joint research in this project.
Specifically, the subtasks in Task 1 on Web-based CAD Compute Center will require the parallel and distributed programming tools (namely, the compilers and visualization tools) developed in Task 3. They will also require the efficient handling of large CAD databases generated from large circuit files, and checkpoint files from simulation, and will use the scalable file servers subtasks in Task 2. In addition, the subtasks will provide input to the educational Task 4, in the form of course materials for the C91, C57, C61, C62, D58 and D59 courses. The subtasks within Task 1 will interact with each other. Using the Web-based CAD computing subtask, we will make available the parallel and distributed CAD tools task, the logic emulation subtask and the low-power CAD tool subtask to the internet. In addition, we will explore parallel algorithms for the low-power design subtask, and the technology mapping and place and route problems of the logic emulation subtask on a network of workstations.
The subtasks in Task 2 on file systems and data management for high-performance distributed computing will support the distributed CAD algorithms subtask of Task 1, and the parallel and distributed programming tools of Task 3. Task 2 will provide input to the educational Task 4 in the form of course materials for the C58, D55, E10 courses. The subtasks of Task 2 will interact among themselves. The runtime optimization subtask will work with the scalable file systems work to provide an efficient parallel I/O operations integrated with file systems.
The subtasks in Task 3 on parallel and distributed programming support tools will support the distributed CAD tools in Task 1. It will also leverage off the scalable file systems and the runtime optimizations subtasks in Task 2. Task 3 will provide the input for course materials for the C58, D52, D55, and E10 courses. Within Task 3, the subtask on domain decomposition techniques for parallel applications will provide strategies for automated compiler techniques for distributed environments. The compiler techniques for out-of-core applications will be extensions of the compiler techniques for distributed environments. The interactive visualization subtask will provide a visualization front-end to the other subtasks.
The subtasks in Task 4 on Undergraduate and Graduate
education will leverage off the latest research results
in the other three tasks as outlined above.
For example, the C91, C57, D58 and D59 courses
will leverage off Task 1,
the C58, D55 courses will leverage off Task 2,
and the C58, D55, D58 courses will leverage off Task 3.
We will involve undergraduates in the research through the R.E.U. outreach
programs.