Northwestern University

PACT Compiler

High-level synthesis for low power.

While there is a trend to add ever more functionality onto chips in the form of entire systems-on-a-chip (SOC), the design times for SOCs are very large. Hence there is a need to develop system level design tools that can take high-level descriptions of SOC designs in languages such as C and map them automatically into hardware.

Complex SOC chips containing billions of transistors, operating at frequencies of more than 10 GHz, consume a lot of power.    There is clearly a need to develop tools to design low power chips. Some example applications needing low power solutions are shown below.

The objectives of the PACT compiler are: (1) to reduce design times of complex SOCs by allowing users to specify their  algorithms in C, and automatically synthesizing hardware designs onto SOCs consisting of embedded processors, FPGAs and ASICs. (2) to explicitly address low power issues during the high-level synthesis stages.

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To contact us:

Phone: 847-491-4118
Fax: 847-467-4455

Electrical and Computer Engineering
Northwestern University
2145 Sheridan Road
Evanston, IL-60208