- Compiling Matlab Programs to ScaLAPACK: Exploiting Task and Data Parallelism.

S. Ramaswamy, E. W. Hodges, and P. Banerjee, in Proceedings of the International Parallel Processing Symposium, Honolulu, HI, April 1996.

- A MATLAB Compiler for Distributed Heterogeneous Reconfigurable Computing Systems, P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, and D. Zaretsky,
*Int. Symp. on FPGA Custom Computing Machines (FCCM-2000)*Napa Valley, CA, Apr. 2000.- M. Haldar, A. Nayak, A. Kanhere, P. Joisha, N. Shenoy, A. Choudhary, P. Banerjee, ``Match Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel,''
*International Conference on Parallel Processing (ICPP-2000)*, Aug. 2000, Toronto, CANADA.- A. Nayak, M. Haldar, A. Kanhere, P. Joisha, N. Shenoy, A. Choudhary, P. Banerjee, ``A Library-Based Compiler to Execute MATLAB Programs on a Heterogeneous Platform,''
*Proc. Parallel and Distributed Computing Systems (PDCS-2000)*, Las Vegas, NV, August 2000.### General Compiler Papers

- The PARADIGM Compiler for Distributed-Memory Multicomputers. [300K]

P. Banerjee, J. A. Chandy, E. W. Hodges, J. Go. Holm, A. Lain, D. J. Palermo, S. Ramaswamy, E. Su,

in*IEEE Computer*, Vol. 28, No. 10, pages 37-47, October 1995.

- A C Compiler for a Processor with Reconfigurable Logic, Alex Zhi Ye, M.S. Thesis, Technical Report, Center for Parallel and Distributed Computing, Northwestern University, CPDC-TR-9906-009, June 1999.

- A C Compiler for a Processor with a Reconfigurable Functional Unit, Z. Ye, N. Shenoy, and P. Banerjee,
*Proc. ACM/SIGDA Symposium on Field Programmable Gate Arrays*, Monterey, CA, Feb. 2000.- CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Unit, Z. Ye, P. Banerjee, S. Hauck, and A. Moshovos,
*International Symposium on Computer Architecture*, Toronto, CANADA, June 2000.### Compiler Optimizations

- A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. [235K]

S. Ramaswamy, S. Sapatnekar, and P. Banerjee, IEEE Trans. Parallel and Distributed Systems, Vol. 8, No. 11, pp. 1098-1116, November 1997.- Symphany: A System for Automatic Synthesis of Adaptive Systems, [106K] U. Nagaraj Shenoy, A. Choudhary, P. Banerjee, Technical Report, Center for Parallel and Distributed Computing, Northwestern University, CPDC-TR-9903-002, Mar. 1999.

- An MILP Based Algorithm for Automatic System Level Synthesis, [108K] U. Nagaraj Shenoy, A. Choudhary, P. Banerjee, Technical Report, Center for Parallel and Distributed Computing, Northwestern University, CPDC-TR-9903-003, Mar. 1999.

- A System-Level Synthesis Algorithm with Guaranteed Solution Quality, N. Shenoy, A. Choudhary, and P. Banerjee,
*Proc. Design Automation and Test in Europe (DATE 2000)*, Paris, FRANCE, March 27-30, 2000.- M. Kandemir, A. Choudhary, N. Shenoy, J. Ramanujam, and P. Banerjee, "A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests,"
*Proc. International Conference on Supercomputing(ICS-98)*, Melbourne, AUSTRALIA, July 1998.- M. Kandemir, J. Ramanujam, A. Choudhary, P. Banerjee, "An Iteration Space Transformation Algorithm Based on an Explicit Data Layout Representation for Optimizing Locality,"
*Proc. Workshop on Languages and Compilers for Parallel Computing (LCPC-98)*, Chapel Hill, NC, Aug. 1998.- M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "Improving locality using loop and data transformations in an integrated framework" Proc. 31st Int. Symp. on Micro-Architecture (MICRO-31), Dallas, Texas, Dec. 1998.
- M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, ``A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality,'' Proc. 1999 International Parallel Processing Symposium (IPPS'99)}, San Juan, Puerto Rico, April 1999.
### Testbed, Libraries and Applications

- A Hardware Testbed for Distributed Heterogeneous Adaptive Computing, C. Bachmann, M.S. Thesis, Technical Report, Center for Parallel and Distributed Computing, Northwestern University, CPDC-TR-9905-007, May. 1999.

- Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB, S. Periyacheri, M.S. Thesis, Technical Report, Center for Parallel and Distributed Computing, Northwestern University, CPDC-TR-9905-008, May. 1999.

- Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB, S. Periyayacheri, A. Nayak, A. Jones, N. Shenoy, A. Choudhary, and P. Banerjee, Proc. 11th IASTED Parallel and Distributed Computing and Systems Conference (PDCS'99)}, Cambridge, MA, Nov. 1999.
### Fast CAD Algorithms for FPGAs

- V. Boppana, P. Saxena, P. Banerjee, W. K. Fuchs, and C. L. Liu, ``A Parallel Algorithm for the Technology Mapping of LUT-based FPGAs,''
*Proc. EUROPAR-96 Workshop on Parallel Nonnumerical Algorithms*, Lyon, FRANCE, Aug. 1996.- Parallel Algorithms for FPGA Placement, A M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee,
*Proc. The Great Lakes Symposium on VLSA (GVLSI 2000)*, Chicago, IL, March 2000.- V. Kim, P. Banerjee, K. De, ``Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations,''
*International Conference on Parallel Processing (ICPP-2000)*, Aug. 2000, Toronto, CANADA (submitted Jan. 2000).- Compiling Matlab Programs to ScaLAPACK: Exploiting Task and Data Parallelism.