Taking advantage of these opportunities along with our past ILP compilation experience, we propose Reduced Configuration Space Processor (RCSP), a parameterized family of reconfigurable processor architectures for high performance embedded system development. The RCSP execution model is a novel extension to the traditional ILP execution model, in that, the data-paths and the execution unit resources for an RCSP machine are dynamically reconfigurable under the control of the executing program. We suggest one possible micro-architecture for the RCSP model, which also serves as a target for our planned compilation environment.

Based on RCSP, we have identified the software architecture to provide a complete embedded system development framework composed of

Concurrently, we have made progress in characterizing instruction scheduling optimizations for program graphs with real-time constraints, targeted towards ILP processors which will be further extended to this domain. We are also developing a compilation environment that can take a high-level language program specified in C or C++ for example, and automatically generate code to run on the RCSP. We anticipate that this environment will help cut down software development times significantly, when compared to its DSP counterparts.

We shall present the processor architecture and compilation framework along with some preliminary performance estimates for a few key applications.

Unfortunately, a workstation's poor interaction with a network interface (NI) significantly impedes harnessing the benefits of a SAN. An NI is a device that allows a workstation to send and receive messages from a network. Conventional workstation NIs suffer from several sources of high latency because they were designed with an interface similar to a disk's interface.

In this presentation, I revisit memory hierarchy design and view memory as an inter-operation communication agent: memory is often used to communicate values among program operations. This perspective exposes limitations that are inherent in the use of an address based memory hierarchy. To overcome these limitations I introduce Memory Dependence Prediction, a technique that transparently captures the communication relationships among memory accessing operations. Memory dependence prediction enables a number of novel techniques that improve upon traditional memory hierarchies. In this presentation I will focus on the following two techniques: (1) Dynamic Speculation and Synchronization, and (2) Speculative Memory Cloaking. The first technique exposes the parallelism that is hindered by the use of addresses. The second technique modifies memory operations as they are encountered for execution so that they can communicate through a low latency communication mechanism.

This talk will be presented in two parts. In the first part, I will introduce the Non-Temporal Streaming (NTS) Cache. The NTS Cache is an example of multi-lateral cache structures that partition the first level (L1) cache into multiple subcaches. For these designs, the data reference stream of a program is subdivided into appropriate classes, and each class is mapped into a specific subcache whose management policy is more suitable for the access patterns and/or usage characteristics of that class. This sort of selective organization and caching actively retains more useful data in the L1 cache structure, which translates into more cache hits, less cache-memory bus contention, and overall improvement in the average data access time. The NTS Cache utilizes data reuse information for intelligent data placement and active management of its 2-unit lateral structure. I will compare and contrast the NTS Cache with other proposed multi-lateral cache designs, and also show that the multi-lateral design approach generally provides an attractive alternative to the current trend of increasingly large but poorly managed caches.

The second part of the talk will explore the performance and limitations of current approaches to multiple data supply. Currently, multibanking and multiporting by replication are the two popular and implementable approaches to providing multiple ports to the data cache. However, these approaches do not appear scalable with increasing data access parallelism. Whereas the multibanking technique suffers substantial performance degradation because of bank conflicts, multiporting by replication is die area limited and plagued by the need to broadcast stores for coherence. Analysis of the average SPEC95 memory reference stream, however, reveals that a greater majority of all conflicts in a multibank cache is as a result of consecutive references that map into the same cache line of the same cache bank. I will introduce the Locality-Based Interleaved Cache (LBIC), which is built on traditional multibanking and employs limited multiporting in exploiting same line spatial locality. Our detailed simulation results suggest that the LBIC structure is capable of outperforming current multiporting approaches.