In this continuing research grant from DARPA, we will develop scalable, parallel algorithms for VLSI CAD applications on a wide range of parallel platforms, including the 16 processor IBM SP-2 distributed memory message-passing multicomputer, an 8-processor IBM J-40 shared memory multiprocessor, an 8-processor SGI Origin 2000 distributed shared memory multiprocessor, and a network of 20 high-performance HP workstations. The applications that will be parallelized include (1) power estimation of combinational and sequential circuits, (2) extraction of resistance and capacitance of complex 3-dimensional interconnects in future sub-micron VLSI designs, (3) low-power logic synthesis of combinational and sequential circuits, (4) formal verification of combinational and sequential circuits, and (5) high-level synthesis of data-flow graphs for datapaths.