COURSE
TITLE: ECE 362 Computer Architecture Project
CATALOG
DESCRIPTION: Quarter
long team project that entails designing a processor for a complete Instruction
Set. Involves ISA design, design of components, datapath and control for a
pipelined processor to implement the ISA. The design is performed using
industry strength design tools and VHDL is used as the design specification
language. The design is evaluated using benchmark programs for correctness and
performance.
REQUIRED
TEXTS:
D. Patterson and J. Hennessey, Computer Organization and Design: The
Hardware/Software Interface, Morgan Kaufmann, 3rd edition, 2004.
Sailer and Kaeli, The DLX Instruction Set
Architecture Handbook, Morgan Kaufmann.
REFERENCE
TEXTS:
J. Hennessey and D. Patterson, Computer Architecture: A Quantitative
Approach, Morgan Kaufmann, Third edition, 2002.
COURSE
COORDINATORS: Alok Choudhary
COURSE
GOALS: To learn designing and implementing processor
architecture and learn to work in design teams. To understand the design process
based on requirements and then implementing and evaluating the design using
tools.
PREREQUISITES:
ECE 361
PREREQUISITES
BY TOPIC:
1. Instruction
Set Architecture
2. Understanding
adders, multipliers and dividers
3. Datapath,
Control, Pipelining
DETAILED
COURSE TOPICS:
Week
1: Form teams. Understand project. Learn
instruction set for which processor will be designed.
Week
2: Each team presents a "first" plan for
the processor design, validation and evaluation. Begin to assign OPCODES to
ISA.
Week
3: Present a refined plan of processor. Start
implementing components for ALU and control using design tools and VHDL.
Week
4: Present the progress in previous week and
describe how the problems faced during last week were solved. Describe progress
on component implementation. Present plan for component integration.
Week
5: Present the progress in previous week and
describe how the problems faced during last week were solved. Describe progress
on component implementation. Present the final design of the processor including
control. Midterm presentations on the design.
Week
6: Present the progress in previous week and
describe how the problems faced during last week were solved. Describe progress
on component implementation. Demonstrate progress on integration of components.
Present the testing of components and overall test and evaluation plan. Adapt
application codes to be evaluated.
Week
7: Present the progress in previous week and
describe how the problems faced during last week were solved. Describe progress
on integration. Demonstrate the current design for initial evaluation.
Week
8: Present the progress in previous week and
describe how the problems faced during last week were solved. Demonstrate
simple programs running against the processor simulator (written in VHDL).
Week
9: Present the progress in previous week and
describe how the problems faced during last week were solved. Demonstrate bug
fixes and performance enhancements.
Week
10: Present the progress in previous week and
describe how the problems faced during last week were solved. Demonstrate the
final design against benchmark programs, Present the overall design report.
COMPUTER
USAGE: Students use Mentor Graphics design tools and
VHDL to implement a pipelined processor.
PROJECT:
The class is a quarter long team project to design a pipelined processor.
GRADES:
Homeworks/Weekly Presentations - 25 %
Project-Final Design - 75 %
COURSE
OBJECTIVES: When a student completes this course, s/he should be able to:
1. Understand
the design process for computers and learn how to work in teams to achieve the
goals of the project.
2. Understand
the architecture of a basic computer system and its components, and the role of
performance in designing computer systems.
3. Understand
how to design and instruction set and its impact on processor design. To design
ALU and processor datapath and control. Design pipeline processor including
datapath and control, and design to detect and resolve hazards.
4. Understand
how to use CAD tools to design a processor.
ABET CONTENT CATEGORY: 100% Engineering (Design component).