COURSE TITLE: ECE 361 Computer Architecture-I

 

CATALOG DESCRIPTION:  Design and understanding of the computer system as a whole unit. Performance Evaluation and its role in computer system design; Instruction Set Architecture design, Datapath design and optimizations (e.g., ALU); Control design; Single cycle, multiple cycle and pipeline implementations of processor; Hazard detection and forwarding; memory hierarchy design; Cache memories, Virtual memory, peripheral devices and I/O.

 

REQUIRED TEXTS:

 

1.      Class notes (copies of lecture transparencies) handed out to students.

2.      D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann, 3rd edition, 2004..

 

REFERENCE TEXTS:

 

COURSE COORDINATORS: Alok Choudhary

 

COURSE GOALS:

 

To teach designing a complete computer system. Includes designing instruction set architecture, datapaths, control, memory hierarchy including cache memories, virtual memory and I/O systems.

 

PREREQUISITES: ECE 205 and 303

 

PREREQUISITES BY TOPIC:

 

1.      Basic logic design

2.       Understanding adders, multipliers and dividers

3.      Assembly language

 

DETAILED COURSE TOPICS:

 

Week 1: Introduction: Components of a computer system. Evolution of Technology. Factors affecting computer systems design (e.g., technology, applications, performance requirements). READING: Chapter 1.

 

Week 2: Impact of performance in computer system design. Measuring performance, performance metrics, interpreting performance, selecting applications and programs for performance evaluation, comparing and summarizing performance. Benchmarks (SPEC 92) and their results on some real machines. How not to evaluate performance. READING: Chapter 2.

 

Week 3: Instruction Set Architecture design. The role of an instruction set. interface between hardware and software; issues to consider when designing an instruction set; addressing modes. READING: Chapter 3.

 

Week 4: Arithmetic and Logic Units (ALU) for computers. Number system, addition and subtract, adders; multiplication and multipliers; division and dividers; floating point numbers and floating point units; Examples from existing systems. READING: Chapter 4.

 

Week 5: Processor Design. Datapath and control; single cycle design and implementation; simplifying control design; multicycle implementation of datapath and control; example from a real system. READING: Chapter 5.

 

Week 6: Pipelining. Basic concepts in pipelining; datapath for pipeline processor implementation, data hazard and forwarding, data hazard and stalling; control design for pipelines, superscaler design; Examples. READING: Chapter 6.

 

Week 7: Memory Hierarchy: Cache memories. Introduction to caches, measuring and improving performance of caches; design alternatives, direct map, associative caches; replacement policies; examples. READING Chapter 7.

 

Week 8: Virtual Memory: basic design, address translation, placement and replacement; cost and performance issues; common framework for memory hierarchies, Translation Lookaside Buffers. READING Chapter 7.

 

Week 9: Input-Output and Peripheral Devices. I/O performance and measures, technology and characteristics of disks. Busses and protocols. Connecting I/O devices to memory and processor. READING Chapter 8.

 

Week 10: I/O systems design. RAIDs. Memory bandwidth and bus bandwidth requirements for graphics. Example of a typical I/O system. Introduction to multiprocessors. Summary/ READING: Chapter 8 and 9.

 

COMPUTER USAGE: Students use Mentor Graphics design tool to implement a simple single cycle processor with limited instruction set. Use processor simulators to learn and evaluate working of processors. Cache simulators to evaluate cache memory performance.

 

PROJECT: A quarter long project that entails designing a single cycle processor using mentor graphics tool and its evaluation using simple programs. Each week students submit progress on additions to the design.

 

GRADES:

Five homeworks - 20 % 

Project - 30 %

Midterm exam - 20%

Final exam - 30%

 

COURSE OBJECTIVES: When a student completes this course, s/he should be able to:

 

1.      Understand the architecture of a basic computer system and its components, and the role of performance in designing computer systems.

2.      Understand how to design and instruction set and its impact on processor design. To design ALU and processor datapath and control.

3.      Design pipeline processor including datapath and control, and design to detect and resolve hazards.

4.      Understand memory hierarchy design and its impact on overall processor performance. Design cache memory based on the characteristics of the expected workload. Understand the workings of virtual memory and efficient design for TLBs

5.      Understand the I/O system and its design. Be Knowledgeable about Busses and bandwidth requirements to support heterogeneous I/O devices. Understand the disk technology and its impact on performance.

 

ABET CONTENT CATEGORY:  100% Engineering (Design component).