ANCHOR 2005 Final Program

Saturday, June 4, 2005

9:10am – 9:20am	Opening Remarks
9:20pm – 10:30am	Session 1: Performance Evaluation
10:30am – 11:00am	Coffee Break
11:00am – 12:20pm	Session 2: Hardware
12:20pm –	Lunch

Session 1: Performance Evaluation

9:20am – 10:30am

Good Memories: Enhancing Memory Performance for Precise Flow Tracking (slides: pdf)

Boris Grot and William Mangione-Smith, Electrical Engineering Department, University of California - Los Angeles

An Evaluation of the Scalable GigaNetIC Architecture for Access Networks (slides: pdf)

Jörg-Christian Niemann, Mario Porrmann, Heinz Nixdorf Institute, University of Paderborn; Christian Sauer, Corporate Research, Infineon Technologies; Ulrich Rückert, Heinz Nixdorf Institute, University of Paderborn

Evaluation of Direct-to-Cache Transfer during Receive Operations in a Message Passing Environment (slides: pdf)

F. Khunjush and N. J. Dimopoulos, Department of Electrical and Computer Engineering, University of Victoria

Session 2: Hardware

11:00am – 12:20am

Efficient Checksum Calculation using Reduction Trees (slides: pdf)

Kent Wires, Dale Parson and Jesse Thilo, Agere Systems

Multiple-Valued Logic Buses for Reducing Bus Size, Transitions and Power in Deep Submicron Technologies (slides: pdf)

Emre Özer, ARM Ltd.; Resit Sendag, Department of Electrical and Computer Engineering, University of Rhode Island; David Gregg, Department of Computer Science, Trinity College

Stream Architecture for High Speed Packet Inspection (slides: pdf)

Yu-Kuen Lai and Gregory T. Byrd, Department of Electrical and Computer Engineering, North Carolina State University

High-Performance Context-Free Parser for Polymorphic Malware Detection (slides: pdf)

Young H. Cho and William H. Mangione-Smith, Electrical Engineering Department, University of California - Los Angeles