ANCHOR 2005 Advanced Networking and Communications Hardware Workshop http://www.ece.northwestern.edu/anchor Held in conjunction with the 32^nd Annual International Symposium on Computer Architecture (ISCA 2005) Madison, Wisconsin, June 4-8 2005

Organizers: v Taskin Kocak University of Central Florida tkocak@cs.ucf.edu v Gokhan Memik, Northwestern University memik@ece.northwestern.edu

Program Committee: v Brad Calder, UCSD v Maria Gabrani, IBM Research – Zurich v Jorge García, UPC v Mark Heinrich, UCF v Dirk Hoenicke, IBM T.J. Watson v Bill Mangione-Smith, UCLA v Steve Melvin, O'M&M v Christian Sauer, Infineon v Raj Yavatkar, Intel

Workshop Overview:

The rapid expansion of networking applications and data traffic are leading to new specialized network component designs that would keep up with the growing field of networking and communications. Network component design becomes more challenging as the performance and usage of communication networks increase. This workshop focuses on the architectural design approaches for packet-switched networks. From sensor to storage area networks, packet-switched networks are utilized in a wide range of system domains. Furthermore, the workshop aims at providing a forum for scientists and engineers from academia and industry to discuss their latest research on emerging network services.

There is a growing interest in extensible networks, overlay networks, and grid computing. Higher layer processing built in hardware can powerfully support these networks and computational styles. This year’s workshop will be looking for contributions that will benefit these communities.

Workshop Topics:

Topics of particular interest include, but are not limited to:

- Switch and router architectures (including optical and fiber channel networks)

- Communications and network processors

- Co-processors (classification, search engine, traffic manager, etc.)

- Specialized offload engines (protocol offload engines, I/O adapters, etc.)

- Architectures for security applications

- Architectures for processor-memory interconnection

- Hardware accelerators for emerging network services (overlay, extensible, grid computing, etc.)

- Application-specific designs (compression, QoS, etc.)

- Power-efficient architectures

- High-level software for networking hardware

Submission Guidelines:

- Submit a 200-word abstract including title and complete author list in email (plain text preferred) to anchor@ece.northwestern.edu by March 25^th, 2005.

- Submit a 6000-word manuscript in email (pdf or ps format) to anchor@ece.northwestern.edu by April 1^st, 2005.

Notification of acceptance/rejection will be sent out on May 2^nd.

Proceedings are planned to be published in a Lecture Notes in Computer Science (LNCS) series by Springer soon after the workshop.