As in other engineering disciplines, many problems in VLSI CAD are optimization problems. How to effectively solve them is a question of both practical importance and intellectual depth. What is the difference between optimization problems and non-optimization problems? Shall we optimize or not optimize? In this talk, I will discuss a couple of VLSI CAD problems and their algorithm design. The problems include logic gate sizing for noise control and circuit retiming for clock period minimization. They are important in CAD and the algorithms we designed are provably optimal and efficient. On the other hand, they can be viewed as case studies for algorithm design methodologies. I will also share the joy and lessons I learned from them.