ANCHOR 2004 Final Program
Saturday, June 19, 2004
|
1:00pm – 1:05pm |
Opening Remarks |
|
1:05pm – 2:45pm |
Session 1: Architectures |
|
2:45pm – 3:15pm |
Coffee Break |
|
3:15pm – 4:05pm |
Session 2: Performance and Modeling |
|
4:05pm – 4:15pm |
Short Break |
|
4:15pm – 5:30pm |
Session 3: Hardware |
1:05pm – 2:45pm
Efficient
Caching Techniques for Server Network Acceleration
Li Zhao, Department of Computer Science -
University of California; Srihari Makineni, Ramesh Illikkal, Ravi Iyer, Communications Technology Lab - Intel ;Laxmi Bhuyan, Department of Computer Science - University
of California
Pipelining
vs. Multiprocessors – Choosing the Right Network Processor System Topology
Ning
Weng and Tilman Wolf, Department of Electrical and Computer Engineering -
University
of Massachusetts at Amherst
The
Performance Potential of an Integrated Network Interface
Nathan L. Binkert, Ronald G. Dreslinski, Erik G. Hallnor,
Lisa R. Hsu, Steven E. Raasch, Andrew L. Schultz, Steven K. Reinhardt,
Department of Electrical Engineering and Computer Science - University of
Michigan
Jürgen Foag and Roman Koch, Institute of Computer
Engineering - University of Luebeck
3:15pm – 4:05pm
Parallel Decompositions of a
Packet-Processing Workload
Elizabeth Seamans and Mendel Rosenblum, Department of Computer Science - Stanford University
Developing an IP-DSLAM Benchmark for Network Processors
Gunnar Hagen, Infineon Technologies; Jörg-Christian
Niemann, Mario Porrmann, Heinz Nixdorf Institute and Department of Electrical
Engineering - University of Paderborn; Christian Sauer, Infineon Technologies; Adrian Slowik, Michael
Thies, University of Paderborn
4:15pm – 5:30pm
Real-time
Resource Allocators in Network Processors using FIFOs
A
Large-Scale Hardware Timer Manager
Silvio
Dragone, Andreas Döring, IBM Research Zurich; Rainer Hagenau, Institute of
Computer Engineering - University of Luebeck
A
Case for Asynchronous Microengines for Network Processing