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Arindam Mallik PhD Candidate, Computer Engineering Email : arindam at eecs dot northwestern dot edu Voice : +1-847-467-4610 (o) Erdos Number : 3 |
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Arindam graduated from NU on June, 2008. At present, he is working as a specialist researcher at IMEC, Belgium. |
| Resume | Research Statement | Publications | Research Summary | Education | Academic Genealogy |
Resume |
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Research Statement |
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| Microsoft Word Format | PDF Format |
| Research Summary |
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Holistic Computer Architecture, Micro-architecture, Network Processors, Reliability in High Performance Computing I am a computer architect specializing in system architectures that utilize the characteristics of applications, users, and materials in a holistic manner. Computer Architecture serves as an interface between technology trends and marketplace demands. Traditionally, a computer system is usually represented as consisting of five abstraction levels: hardware, firmware, assembler, operating system and applications. My research questions this fundamental definition. Instead of viewing computer architecture as an interface, I aim at introducing a holistic view on computing that involves users, applications, as well as materials. Specifically, I am working on architectural optimizations that consider two new layers lying at two extreme ends of the current set of abstraction levels – users and materials. As we move into deeper sub-micron technologies, the complexity of pushing the performance of processors further faces important obstacles. I tried to invent methods that go beyond the traditional architectural approaches to increase performance. Most importantly, I argued that the collaboration of several layers (e.g., circuits and architectures) is likely to result in architectures that are not possible otherwise. For example, applications lie at the top of the whole spectrum for a computer architect. In other words, architects look into application characteristics and optimize the performance of their system accordingly. The ever-increasing need for improvement in system performance and power utilization led me to believe that we need to look beyond the application level to utilize the system resources intelligently and efficiently. For example, my recent work on user-aware power optimization shows that by considering the user satisfaction during system configuration can result in significant improvements [J1, C1]. On the other side of the spectrum, analysis of the materials that lie at the lowermost end of the abstraction level opens up a number of opportunities to optimize the system performance. In general, the layered approach is not limited to architects. Similarly, circuit designers also have to be conservative because of their own layered view on design, i.e., circuit designers typically consider the worst-case scenario to predict the default voltage properties of a processor chip. The hard constraint of reliability has created a gap between the default value and the threshold where a circuit can work flawlessly. In a recent work, I have shown that by customizing the system configuration to remedy the effects of process variations can improve the architecture performance [C1]. A final aspect of the holistic computing is the consideration of system properties during the architectural design process. I have shown that treating the correctness as an objective can improve the system performance with noted reductions in power consumption. Specifically, I have developed a scheme for networking systems that take advantage of the system-level resiliency [J2, C5, C7]. If a system’s inherent robustness can be used to correct faults introduced due to loosened reliability, much power and performance gain can be achieved. I have proposed novel schemes that utilize system attributes to ensure correctness of an application. It creates an opportunity to improve performance in lieu of loosened reliability. The results obtained from these research works have shown that the idea of the “holistic computer architectures” can be utilized by various processor architectures.
My long
term research goal is to establish a framework for the holistic
architectures. So far, I have contributed to the following results towards
this goal: Concentration : Holistic Computer Architecture Advisor : Dr. Gokhan Memik Precision Analysis in High Level Synthesis I have worked in the DARPA funded PACT (Power Aware Architectural and Compilation Techniques) Project under the guidance of Prof. Prith Banerjee for my Master's degree. An important trend in the next generation embedded systems domain is the emerging emphasis on the design of low-power systems. Most practical ASIC designs of embedded applications are limited to fixed-point arithmetic owing to the cost and complexity of floating point hardware. One way to reduce power in an ASIC implementation is to reduce the bit-width precision of computation units. I investigated system level tradeoffs of round-off errors in an algorithm with the area and power consumption of the hardware implementation by varying the bit-width precision of individual operators. Concentration : Power and Area Optimization in VLSI circuits Advisor : Prof. Prith Banerjee |
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Copyright@2004-15, Arindam
Mallik, EECS, NU, Evanston, IL 60208, USA
Last Updated -
Tuesday March 02, 2010
